ZHCSKL5D November 2019 – March 2022 LMX2694-EP
PRODUCTION DATA
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| SYNC AND SYSREFREQ TIMING | ||||||
| tSETUP | Setup time for pin relative to OSCIN rising edge | See Figure 6-1 | 9 | ns | ||
| tHOLD | Hold time for pin relative to OSCIN rising edge | 4 | ns | |||
| DIGITAL INTERFACE WRITE SPECIFICATIONS | ||||||
| fSPIWrite | SPI write speed | tCWL + tCWH ≥ 25 ns | 40 | MHz | ||
| tCE | Clock to enable low time | See Figure 6-2 | 5 | ns | ||
| tCS | Data to clock setup time | 2 | ns | |||
| tCH | Data to clock hold time | 2 | ns | |||
| tCWH | Clock pulse width high | 5 | ns | |||
| tCWL | Clock pulse width low | 5 | ns | |||
| tCES | Enable to clock setup time | 5 | ns | |||
| tEWH | Enable pulse width high | 2 | ns | |||
| DIGITAL INTERFACE READBACK SPECIFICATIONS | ||||||
| fSPIReadback | SPI readback speed | See Figure 6-3 | 40 | MHz | ||
| tCE | Clock to enable low time | 5 | ns | |||
| tCS | Clock to data wait time | 2 | ns | |||
| tCH | Clock to data hold time | 2 | ns | |||
| tCWH | Clock pulse width high | 10 | ns | |||
| tCWL | Clock pulse width low | 10 | ns | |||
| tCES | Enable to clock setup time | 5 | ns | |||
| tEWH | Enable pulse width high | 2 | ns | |||
| tCD | Falling clock edge to data wait time | 8 | ns | |||