The system voltage range of the LM5067 is –9 V to –80 V, with a transient capability to -100 V. Referring to the Functional Block Diagram, Figure 9-1, and Figure 8-2, as the system voltage (V_SYS) initially increases from zero, the external N-channel MOSFET (Q1) is held off by an internal 110 mA pull-down current at the GATE pin. The strong pull-down current at the GATE pin prevents an inadvertent turn-on as the MOSFET’s gate-to-drain (Miller) capacitance is charged. When the operating voltage of the LM5067 (VCC – VEE) reaches the POR_IT threshold (7.7V) the insertion timer starts. During the insertion time, the capacitor at the TIMER pin (C_T) is charged by a 6 μA current source, and Q1 is held off by a 2.2 mA pull-down current at the GATE pin regardless of the system voltage. The insertion time delay allows ringing and transients at V_SYS to settle before Q1 can be enabled. The insertion time ends when the TIMER pin voltage reaches 4 V above VEE, and C_T is then quickly discharged by an internal 1.5 mA pull-down current. After the insertion time, the LM5067 control circuitry is enabled when the operating voltage reaches the POR_EN threshold (8.4 V). As V_SYS continues to increase, the LM5067 operating voltage is limited at ?13 V by an internal zener diode. The remainder of the system voltage is dropped across the input resistor R_IN.

The GATE pin switches on Q1 when V_SYS exceeds the UVLO threshold (UVLO pin >2.5V above VEE). If V_SYS exceeds the UVLO threshold at the end of the insertion time, Q1 is switched on at that time. The GATE pin sources 52 μA to charge Q1’s gate capacitance. The maximum gate-to-source voltage of Q1 is limited by the LM5067’s operating voltage (V_Z) to approximately 13 V. During power up, as the voltage at the OUT pin increases in magnitude with respect to Ground, the LM5067 monitors Q1’s drain current and power dissipation. In-rush current limiting and/or power limiting circuits actively control the current delivered to the load. During the in-rush limiting interval (t2 in Figure 8-2) an internal current source charges C_T at the TIMER pin. When the load current reduces from the limiting value to a value determined by the load the in-rush limiting interval is complete and C_T is discharged. The PGD pin switches high when the voltage at the OUT pin reaches to within 1.25 V of the voltage at the SENSE pin.

If the TIMER pin voltage reaches 4.0V before in-rush current limiting or power limiting ceases (during t2), a fault is declared and Q1 is turned off. See Fault Timer and Restart for a complete description of the fault mode.

Figure 8-2 Power Up Sequence (Current Limit only)