ZHCSP68C December 2021 – October 2022 DRV8328
PRODUCTION DATA
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| VPVDD | Power supply voltage | PVDD | 4.5 | 60 | V | |
| VPVDD_RAMP | Power supply voltage ramp rate at power up | PVDD | 30 | V/us | ||
| VPVDD_RAMP | Power supply voltage ramp rate during operation | PVDD | 4 | V/us | ||
| VBST | Bootstrap pin voltage with respect to SHx | nSLEEP = High, INHx is switching | 4 | 20 | V | |
| IAVDD(1) | Regulator external load current | AVDD | 80 | mA | ||
| ITRICKLE | Trickle charge pump external load current | BSTx | 2 | μA | ||
| VIN | Logic input voltage | DRVOFF, INHx, INLx, nSLEEP | 0 | 5.5 | V | |
| VIN | Logic input voltage | DT, VDSLVL | 0 | 3.4 | V | |
| fPWM | PWM frequency | INHx, INLx | 0 | 200 | kHz | |
| VOD | Open drain pullup voltage | nFAULT | 5.5 | V | ||
| IOD | Open drain output current | nFAULT | -10 | mA | ||
| IGS(1) | Total average gate-drive current (Low Side and High Side Combined) | IGHx, IGLx | 30 | mA | ||
| VCSAREF | Current sense amplifier reference voltage | CSAREF | 2.8 | 5.5 | V | |
| ISO | Shunt amplifier output current | SO | 5 | mA | ||
| VSHSL | Slew Rate on SHx pins | 4 | V/ns | |||
| CBSTx | Capacitor between BSTx and SHx | 4.7 (2) | μF | |||
| CGVDD | Capacitor between GVDD and GND | 130 | μF | |||
| TA | Operating ambient temperature | –40 | 125 | °C | ||
| TJ | Operating junction temperature | –40 | 150 | °C | ||