ZHCSP68C December 2021 – October 2022 DRV8328
PRODUCTION DATA
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Power supply pin voltage | PVDD | -0.3 | 65 | V |
| Bootstrap pin voltage | BSTx | -0.3 | 80 | V |
| Bootstrap pin voltage | BSTx with respect to SHx | -0.3 | 20 | V |
| Bootstrap pin voltage | BSTx with respect to GHx | -0.3 | 20 | V |
| Charge pump pin voltage | CPL, CPH | -0.3 | VGVDD | V |
| Gate driver regulator pin voltage | GVDD | -0.3 | 20 | V |
| Analog regulator pin voltage | AVDD | -0.3 | 4 | V |
| Logic pin voltage (nSLEEP) | nSLEEP | -0.3 | 65 | V |
| Logic pin voltage | DRVOFF, DT, INHx, INLx, nFAULT, VDSLVL | -0.3 | 6 | V |
| High-side gate drive pin voltage | GHx | -8 | 80 | V |
| Transient 500-ns high-side gate drive pin voltage | GHx | -10 | 80 | V |
| High-side gate drive pin voltage | GHx with respect to SHx | -0.3 | 20 | V |
| High-side source pin voltage | SHx | -8 | 70 | V |
| Transient 500-ns high-side source pin voltage | SHx | -10 | 72 | V |
| Low-side gate drive pin voltage | GLx with respect to LSS | -0.3 | 20 | V |
| Transient 500-ns low-side gate drive pin voltage(2) | GLx with respect to LSS | -1 | 20 | V |
| Low-side gate drive pin voltage | GLx with respect to GVDD | 0.3 | V | |
| Transient 500-ns low-side gate drive pin voltage | GLx with respect to GVDD | 1 | V | |
| Low-side source sense pin voltage | LSS | -1 | 1 | V |
| Transient 500-ns low-side source sense pin voltage | LSS | -10 | 8 | V |
| Gate drive current | GHx, GLx | Internally Limited | Internally Limited | A |
| Current sense amplifer reference input pin voltage | CSAREF | -0.3 | 5.5 | V |
| Shunt amplifier input pin voltage | SN, SP | -1 | 1 | V |
| Transient 500-ns shunt amplifier input pin voltage | SN, SP | -10 | 8 | V |
| Shunt amplifier output pin voltage | SO | -0.3 | VCSAREF + 0.3 | V |
| Junction temperature, TJ | –40 | 150 | °C | |
| Storage temperature, Tstg | –65 | 150 | °C | |