ZHCSJ33F December 2015 – May 2019 DRA745 , DRA746 , DRA750 , DRA756
PRODUCTION DATA.
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Figure 7-87, Figure 7-88, and Table 7-133, through Table 7-136 present Timing requirements and Switching characteristics for MMC3 and MMC4 - SD and SDIO SDR12 in receiver and transmitter mode.
| NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
|---|---|---|---|---|---|
| SDR125 | tsu(cmdV-clkH) | Setup time, mmc3_cmd valid before mmc3_clk rising clock edge | 25.99 | ns | |
| SDR126 | th(clkH-cmdV) | Hold time, mmc3_cmd valid after mmc3_clk rising clock edge | 1.6 | ns | |
| SDR127 | tsu(dV-clkH) | Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge | 25.99 | ns | |
| SDR128 | th(clkH-dV) | Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge | 1.6 | ns |
| NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
|---|---|---|---|---|---|
| SDR120 | fop(clk) | Operating frequency, mmc3_clk | 24 | MHz | |
| SDR121 | tw(clkH) | Pulse duration, mmc3_clk high | 0.5*P-0.270 (1) | ns | |
| SDR122 | tw(clkL) | Pulse duration, mmc3_clk low | 0.5*P-0.270 (1) | ns | |
| SDR123 | td(clkL-cmdV) | Delay time, mmc3_clk falling clock edge to mmc3_cmd transition | -19.13 | 16.93 | ns |
| SDR124 | td(clkL-dV) | Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition | -19.13 | 16.93 | ns |
| NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
|---|---|---|---|---|---|
| SDR125 | tsu(cmdV-clkH) | Setup time, mmc4_cmd valid before mmc4_clk rising clock edge | 25.99 | ns | |
| SDR126 | th(clkH-cmdV) | Hold time, mmc4_cmd valid after mmc4_clk rising clock edge | 1.6 | ns | |
| SDR127 | tsu(dV-clkH) | Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge | 25.99 | ns | |
| SDR128 | th(clkH-dV) | Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge | 1.6 | ns |
| NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
|---|---|---|---|---|---|
| SDR120 | fop(clk) | Operating frequency, mmc4_clk | 24 | MHz | |
| SDR121 | tw(clkH) | Pulse duration, mmc4_clk high | 0.5*P-0.270 (1) | ns | |
| SDR122 | tw(clkL) | Pulse duration, mmc4_clk low | 0.5*P-0.270 (1) | ns | |
| SDR125 | td(clkL-cmdV) | Delay time, mmc4_clk falling clock edge to mmc4_cmd transition | -19.13 | 16.93 | ns |
| SDR126 | td(clkL-dV) | Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition | -19.13 | 16.93 | ns |
Figure 7-87 MMC/SD/SDIOj in - SDR12 - Receiver Mode
Figure 7-88 MMC/SD/SDIOj in - SDR12 - Transmitter Mode