ZHCSJ33F December 2015 – May 2019 DRA745 , DRA746 , DRA750 , DRA756
PRODUCTION DATA.
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| NO. | PARAMETER | DESCRIPTION | MODE | MIN | MAX | UNIT |
|---|---|---|---|---|---|---|
| 1 | tc(AHCLKRX) | Cycle time, AHCLKR/X | 20 | ns | ||
| 2 | tw(AHCLKRX) | Pulse duration, AHCLKR/X high or low | 0.35P (2) | ns | ||
| 3 | tc(ACLKRX) | Cycle time, ACLKR/X | Any Other Conditions | 20 | ns | |
| ACLKX/AFSX (In Sync Mode),
ACLKR/AFSR (In Async Mode), and AXR are all inputs "80M" Virtual IO Timing Mode |
12.5 | ns | ||||
| 4 | tw(ACLKRX) | Pulse duration, ACLKR/X high or low | Any Other Conditions | 0.5R - 3 (3) | ns | |
| ACLKX/AFSX (In Sync Mode),
ACLKR/AFSR (In Async Mode), and AXR are all inputs "80M" Virtual IO Timing Modes |
0.38R (3) | ns | ||||
| 5 | tsu(AFSRX-ACLK) | Setup time, AFSR/X input valid before ACLKR/X | ACLKR/X int | 20.7 | ns | |
| ACLKR/X ext in
ACLKR/X ext out |
3.9 | ns | ||||
| ACLKR/X ext in
ACLKR/X ext out "80M" Virtual IO Timing Modes |
3 | ns | ||||
| 6 | th(ACLK-AFSRX) | Hold time, AFSR/X input valid after ACLKR/X | ACLKR/X int | -1 | ns | |
| ACLKR/X ext in
ACLKR/X ext out |
3.2 | ns | ||||
| ACLKR/X ext in
ACLKR/X ext out "80M" Virtual IO Timing Modes |
3 | ns | ||||
| 7 | tsu(AXR-ACLK) | Setup time, AXR input valid before ACLKR/X | ACLKR/X int | 21.4 | ns | |
| ACLKR/X ext in
ACLKR/X ext out |
3.9 | ns | ||||
| ACLKR/X ext in
ACLKR/X ext out "80M" Virtual IO Timing Modes |
3 | ns | ||||
| 8 | th(ACLK-AXR) | Hold time, AXR input valid after ACLKR/X | ACLKR/X int | -1 | ns | |
| ACLKR/X ext in
ACLKR/X ext out |
3.2 | ns | ||||
| ACLKR/X ext in
ACLKR/X ext out "80M" Virtual IO Timing Modes |
3 | ns |