ZHCSJ33F December 2015 – May 2019 DRA745 , DRA746 , DRA750 , DRA756
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Table 7-37 and Table 7-38 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 7-25, Figure 7-26, Figure 7-27 and Figure 7-28).
| NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
|---|---|---|---|---|---|
| 1 | tCYCH | Read bit window timing | 190 | 250 | µs |
| 2 | tHW1 | Read one data valid after HDQ low | 32(2) | 66(2) | µs |
| 3 | tHW0 | Read zero data hold after HDQ low | 70(2) | 145(2) | µs |
| 4 | tRSPS | Response time from HDQ slave device(1) | 190 | 320 | µs |
| NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
|---|---|---|---|---|---|
| 5 | tB | Break timing | 190 | µs | |
| 6 | tBR | Break recovery time | 40 | µs | |
| 7 | tCYCD | Write bit windows timing | 190 | µs | |
| 8 | tDW1 | Write one data valid after HDQ low | 0.5 | 50 | µs |
| 9 | tDW0 | Write zero data hold after HDQ low | 86 | 145 | µs |
Figure 7-25 HDQ Break and Break Recovery Timing — HDQ Interface Writing to Slave
Figure 7-26 Device HDQ Interface Bit Read Timing (Data)
Figure 7-27 Device HDQ Interface Bit Write Timing (Command / Address or Data)
Figure 7-28 HDQ Communication Timing