ZHCSJ33F December 2015 – May 2019 DRA745 , DRA746 , DRA750 , DRA756
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Table 7-110 presents Timing requirements and Switching characteristics for MMC1 - SDR104 in receiver and transmitter mode (see Figure 7-72 and Figure 7-73)
| NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
|---|---|---|---|---|---|
| SDR1041 | fop(clk) | Operating frequency, mmc1_clk | 192 | MHz | |
| SDR1042H | tw(clkH) | Pulse duration, mmc1_clk high | 0.5*P-0.185 (1) | ns | |
| SDR1042L | tw(clkL) | Pulse duration, mmc1_clk low | 0.5*P-0.185 (1) | ns | |
| SDR1045 | td(clkL-cmdV) | Delay time, mmc1_clk falling clock edge to mmc1_cmd transition | -1.09 | 0.49 | ns |
| SDR1046 | td(clkL-dV) | Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition | -1.09 | 0.49 | ns |
Figure 7-72 MMC/SD/SDIO in - High Speed SDR104 - Receiver Mode
Figure 7-73 MMC/SD/SDIO in - High Speed SDR104 - Transmitter Mode