ZHCSR27D August 2020 – September 2022 BQ79612-Q1 , BQ79614-Q1 , BQ79616-Q1
PRODUCTION DATA
AUX_CELL_HI
| Address | 0x05B2 | |||||||
| Read Only | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
| Name | RESULT[7:0] | |||||||
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| RESULT[7:0] = | The ADC measurement result of the high-byte of the AUXCELL voltage in 2s complement. These AUX_CELL_HI/LO registers will only report AUXCELL voltage measurement if host configures [AUX_CELL_SEL4:0] to lock to a single AUXCELL channel. When host reads this register, the device locks the AUXCELL voltage low-byte from updating until the high-byte and low-byte registers are read. | |||||||
AUX_CELL_LO
| Address | 0x05B3 | |||||||
| Read Only | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
| Name | RESULT[7:0] | |||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| RESULT[7:0] = | The ADC measurement result of the low-byte of the AUX cell voltage in 2s complement. These AUX_CELL_HI/LO registers will only report AUXCELL voltage measurement if host configures [AUX_CELL_SEL4:0] to lock to a single AUXCELL channel. | |||||||