ZHCSR27D August 2020 – September 2022 BQ79612-Q1 , BQ79614-Q1 , BQ79616-Q1
PRODUCTION DATA
When a device detects a fault, the corresponding low-level register bit, including the one in the related bit in the DEBUG_* registers is set. Based on the fault hierarchy relationship, the fault will be reflected in the FAULT_SUMMARY register.
A group of faults can be masked, which the related low-level register flag will still be set, but the fault will not be reflected to the corresponding FAULT_SUMMARY register. The faults can be masked through the FAULT_MSK1 and FAULT_MSK2 registers.
For example, to mask the FAULT_SUMMARY[FAULT_OTUT] being set, host sets FAULT_MSK1[MSK_OT] = 1 and [MSK_UT] = 1.
When fault is masked, it will also prevent the device from asserting the NFAULT pin when the masked fault occurs. See Section 9.3.6.2.3 for details on NFAULT signal.
| Masking Bit Name | Related Low-level Register(s) Affected | FAULT_SUMMARY Register Bit That Will Be Masked | |
|---|---|---|---|
| FAULT_MSK1 | [MSK_PROT] | FAULT_PROT* | [FAULT_PROT] |
| [MSK_UT] | FAULT_UT | [FAULT_OTUT] | |
| [MSK_OT] | FAULT_OT | ||
| [MSK_UV] | FAULT_UV* | [FAULT_OVUV] | |
| [MSK_OV] | FAULT_OV* | ||
| [MSK_COMP] | FAULT_COMP_* | [FAULT_COMP] | |
| [MSK_SYS] | FAULT_SYS | [FAULT_SYS] | |
| [MSK_PWR] | FAULT_PWR* | [FAULT_PWR] | |
| FAULT_MSK2 | [MSK_OTP_CRC] | FAULT_OTP[CUST_CRC][FACT_CRC] | [FAULT_OTP] |
| [MSK_OTP_DATA] | All non-CRC bits in FAULT_OTP, DEBUG_OTP_* | ||
| [MSK_COMM3_FCOMM] | FAULT_COMM3[FCOMM_DET] | [FAULT_COMM3] | |
| [MSK_COMM3_FTONE] | FAULT_COMM3[FTONE_DET] | ||
| [MSK_COMM3_HB] | FAULT_COMM3[HB_FAIL][HB_FAST] | ||
| [MSK_COMM2] | FAULT_COMM2, DEBUG_COMH_*, DEBUG_COML_* | [FAULT_COMM2] | |
| [MSK_COMM1] | FAULT_COMM1, DEBUG_UART_* | [FAULT_COMM1] |