SLUSFR7 August 2025 BQ24810
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Pin Configuration and Functions
- 5 Specifications
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 Device Power Up
- 6.3.2 System Power Selection
- 6.3.3 Current and Power Monitor
- 6.3.4 Processor Hot Indication for CPU Throttling
- 6.3.5 Input Current Dynamic Power Management
- 6.3.6 Two-Level Adapter Current Limit (Peak Power Mode)
- 6.3.7 EMI Switching Frequency Adjust
- 6.3.8 Device Protections Features
- 6.4 Device Functional Modes
- 6.5 Programming
- 6.6
Register Maps
- 6.6.1 Battery-Charger Commands
- 6.6.2 Setting Charger Options
- 6.6.3 ChargeOption1 Register
- 6.6.4 ChargeOption2 Register
- 6.6.5 ChargeOption3 Register
- 6.6.6 ChargeOption4 Register
- 6.6.7 ProchotOption0 Register
- 6.6.8 ProchotOption1 Register
- 6.6.9 ProchotStatus Register
- 6.6.10 Charge Current Register
- 6.6.11 Charge Voltage Register
- 6.6.12 Discharge Current Register
- 6.6.13 Minimum System Voltage Register
- 6.6.14 Input Current Register
- 6.6.15 Register Exceptions
-
7 Application and Implementation
- 7.1 Application Information
- 7.2
Typical Applications
- 7.2.1
Typical System Schematic
- 7.2.1.1 Design Requirements
- 7.2.1.2
Detailed Design Procedure
- 7.2.1.2.1 Adapter Current Sense Filter
- 7.2.1.2.2 Negative Output Voltage Protection
- 7.2.1.2.3 Reverse Input Voltage Protection
- 7.2.1.2.4 Reduce Battery Quiescent Current
- 7.2.1.2.5 CIN Capacitance
- 7.2.1.2.6 L1 Inductor Selection
- 7.2.1.2.7 CBATT Capacitance
- 7.2.1.2.8 Buck Charging Internal Compensation
- 7.2.1.2.9 CSYS Capacitance
- 7.2.1.2.10 Battery Only Boost Internal Compensation
- 7.2.1.2.11 Power MOSFETs Selection
- 7.2.1.2.12 Input Filter Design
- 7.2.1.3 Application Curves
- 7.2.2 Migration from Previous Devices (Does Not Support Battery Only Boost)
- 7.2.1
Typical System Schematic
- 7.3 Power Supply Recommendations
- 7.4 Layout
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RUY|28
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
6.3.6 Two-Level Adapter Current Limit (Peak Power Mode)
An adapter can usually supply current higher than its DC rating for a few milliseconds to tens of milliseconds. The BQ24810 employs two-level input current limit, or peak power mode, to fully utilize the adapter overloading capability and minimize battery discharge. Peak power mode is enabled in REG0x38[13]. The DC current limit, or ILIM1, is the same as adapter DC current DPM, set in REG0x3F(). The overloading current, or ILIM2, is set in REG0x3C[14:11], as a percentage of ILIM1.The maximum ILIM2 regulation is clamped at around 109mV across ACP-ACN voltage due to IC internal implementation. This is 10.9A under 10 mΩ and if higher ILIM2 is needed then smaller RAC have to be used.
With peak power mode enabled, adapter current greater than ILIM1 will not immediately trigger hybrid boost supplement mode. Instead, if the adapter current remains above the ILIM1 (scaled by FDPM_RISE percentage) threshold for 50 uS, peak power mode is entered and the adapter DPM limit is raised to ILIM2 for a period of TOVLD as set in 0x38H [15:14]. During this period, hybrid boost may still be entered if it is enabled and adapter current exceeds ILIM2 (scaled by FDPM_RISE percentage) for a period of FDPM_DEG as set in REG0x37[4:3]. At the end of the TOVLD period, the BQ24810 enters a recovery period where the DPM limit is set to ILIM1 for TMAX – TOVLD. So the longest adapter current overshoot should be FDPM_DEG+TOVLD above ILIM1. TMAX is set in REG0x38[15:14]. Once the full TMAX (overload and recovery periods) has expired, the peak power mode exits, also forcing an exit from hybrid boost mode if it is active. Upon this exit, the BQ24810 will immediately re-enter a new peak power mode cycle if adapter current remains above the ILIM1 (scaled by FDPM_RISE percentage) for the 50 uS qualifying period.
![BQ24810 Two-Level Adapter Current Limit Timing Diagram, REG0x37[8] = 0](/ods/images/SLUSFR7/GUID-A074717A-DBC1-4D11-9FA5-A873A283C2D8-low.gif "BQ24810 Two-Level Adapter Current Limit Timing Diagram, REG0x37[8] = 0")
Figure 6-2 Two-Level Adapter Current Limit Timing Diagram, REG0x37[8] = 0Charging may optionally be disabled (REG0x37[8]=0) during TMAX in order to reduce adapter current during overload condition. If REG0x37[8] is instead set to 1, and if all other conditions for charging are met, including the charge inhibit bit (REG0x12[0]) being set to 0, then charging will resume during TMAX if the adapter current falls below the active current limit, which is ILIM2 during TOVLD and ILIM1 during the subsequent relaxation period.
During the peak power mode overload period ( TOVLD ), the INOM event will not trigger PROCHOT, even if the event is enabled and adapter current exceeds the INOM threshold. The ICRIT event remains active during this time. During the recovery period ( TMAX - TOVLD ), both the INOM and ICRIT events are active if enabled.
The peak power mode timing parameters (TOVLD and TMAX) are not allowed to be changed while peak power mode is enabled. Any write to either 0x38H [15:14] (TOVLD) or 0x38H [9:8] (TMAX) or EN_3L while the peak power mode is enabled (0x38 [13] = 1) will be ignored. In order to change these parameters, the user must first disable peak power mode by writing 0x38 [13] = 0, then update TOVLD and/or TMAX, and then re-enable the peak power mode by writing 0x38 [13] = 1.