SLUSFR7 August 2025 BQ24810
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Pin Configuration and Functions
- 5 Specifications
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 Device Power Up
- 6.3.2 System Power Selection
- 6.3.3 Current and Power Monitor
- 6.3.4 Processor Hot Indication for CPU Throttling
- 6.3.5 Input Current Dynamic Power Management
- 6.3.6 Two-Level Adapter Current Limit (Peak Power Mode)
- 6.3.7 EMI Switching Frequency Adjust
- 6.3.8 Device Protections Features
- 6.4 Device Functional Modes
- 6.5 Programming
- 6.6
Register Maps
- 6.6.1 Battery-Charger Commands
- 6.6.2 Setting Charger Options
- 6.6.3 ChargeOption1 Register
- 6.6.4 ChargeOption2 Register
- 6.6.5 ChargeOption3 Register
- 6.6.6 ChargeOption4 Register
- 6.6.7 ProchotOption0 Register
- 6.6.8 ProchotOption1 Register
- 6.6.9 ProchotStatus Register
- 6.6.10 Charge Current Register
- 6.6.11 Charge Voltage Register
- 6.6.12 Discharge Current Register
- 6.6.13 Minimum System Voltage Register
- 6.6.14 Input Current Register
- 6.6.15 Register Exceptions
-
7 Application and Implementation
- 7.1 Application Information
- 7.2
Typical Applications
- 7.2.1
Typical System Schematic
- 7.2.1.1 Design Requirements
- 7.2.1.2
Detailed Design Procedure
- 7.2.1.2.1 Adapter Current Sense Filter
- 7.2.1.2.2 Negative Output Voltage Protection
- 7.2.1.2.3 Reverse Input Voltage Protection
- 7.2.1.2.4 Reduce Battery Quiescent Current
- 7.2.1.2.5 CIN Capacitance
- 7.2.1.2.6 L1 Inductor Selection
- 7.2.1.2.7 CBATT Capacitance
- 7.2.1.2.8 Buck Charging Internal Compensation
- 7.2.1.2.9 CSYS Capacitance
- 7.2.1.2.10 Battery Only Boost Internal Compensation
- 7.2.1.2.11 Power MOSFETs Selection
- 7.2.1.2.12 Input Filter Design
- 7.2.1.3 Application Curves
- 7.2.2 Migration from Previous Devices (Does Not Support Battery Only Boost)
- 7.2.1
Typical System Schematic
- 7.3 Power Supply Recommendations
- 7.4 Layout
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RUY|28
散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
4 Pin Configuration and Functions
Figure 4-1 RUY Package28-Pin WQFNTop ViewTable 4-1 Pin Functions
| PIN | DESCRIPTION | |
|---|---|---|
| NAME | NO. | |
| ACN | 1 | Input current sense resistor negative input. Place an optional 0.1-μF ceramic capacitor from ACN to GND for common-mode filtering. Place a 0.1-μF ceramic capacitor from ACN to ACP to provide differential mode filtering. |
| ACP | 2 | Input current sense resistor positive input. Place a 0.1-μF ceramic capacitor from ACP to GND for common-mode filtering. Place a 0.1-μF ceramic capacitor from ACN to ACP to provide differential-mode filtering. |
| CMSRC | 3 | ACDRV charge pump source input. Place a 4-kΩ resistor from CMSRC to the common source of ACFET (Q1) and RBFET (Q2) to limit the inrush current on CMSRC pin. |
| ACDRV(BQ24810) | 4 | Charge pump output to drive both adapter input N-channel MOSFET (ACFET) and reverse blocking N-channel MOSFET (RBFET). ACDRV voltage is 6 V above CMSRC when ACOK is HIGH. ACDRV voltage is equal to CMSRC pin when ACOK is low. Place a 4-kΩ resistor from ACDRV to the gate of ACFET and RBFET limits the inrush current on ACDRV pin. |
| ACOK | 5 | Active HIGH AC adapter detection open drain output. It is pulled HIGH to external pull-up supply rail by external pull-up resistor when a valid adapter is present (ACDET above 2.4 V, VCC above UVLO but below ACOV and VCC above BAT). If any of the above conditions is not valid, ACOK is pulled LOW by internal MOSFET. Connect a 10-kΩ pull-up resistor from ACOK to the pull-up supply rail. |
| ACDET | 6 | Adapter detection input. Program adapter valid input threshold by connecting a resistor divider from adapter input to ACDET pin to GND pin. When ACDET pin is above 0.6 V and VCC is above UVLO, REGN LDO is present, ACOK comparator, input current buffer (IADP), discharge current buffer (IDCHG), independent comparator, and power monitor buffer (PMON) can be enabled with SMBus. When ACDET is above 2.4 V, and VCC is above SRN but below ACOV, ACOK goes HIGH. Total resistance from Adapter to ACDET to GND varies from 100 kΩ to 1 MΩ. |
| IADP | 7 | Buffered adapter current output. VIADP = 20 or 40 × (VACP – VACN) The ratio of 20x and 40x is selectable with SMBus. Place 100-pF (or less) ceramic decoupling capacitor from IADP pin to GND. This pin can be floating if this output is not in use. |
| IDCHG | 8 | Buffered discharge current. VIDCHG = 8 or 16 × (VSRN – VSRP) The ratio of 8x or 16x is selectable with SMBus. Place 100-pF (or less) ceramic decoupling capacitor from IDSCHG pin to GND. This pin can be floating if this output is not in use. |
| PMON | 9 | Buffered system power output. The output current is proportional to the total power from the adapter and battery together. The ratio is selectable through SMBus. Place a resistor from PMON pin to GND to generate PMON voltage. Place a 100-pF (or less) ceramic decoupling capacitor from PMON pin to GND. The pin voltage is clamped to a maximum of 3.3 V. |
| PROCHOT | 10 | Active low, open-drain output of the processor hot indicator. The charger IC monitors events like adapter current, battery discharge current. After any event in the PROCHOT profile is triggered, signal is asserted low. Connect a 500-Ω pull-up resistor from PROCHOT pin to the CPU Vtt supply rail (commonly 1.05 V.) |
| SDA | 11 | SMBus open-drain data I/O. Connect to SMBus data line from the host controller or smart battery. SMBus communication starts when VCC is above UVLO. Connect a 10-kΩ pull-up resistor according to SMBus specifications. |
| SCL | 12 | SMBus open-drain clock input. Connect to SMBus clock line from the host controller or smart battery. SMBus communication starts when VCC is above UVLO. Connect a 10-kΩ pull-up resistor according to SMBus specifications. |
| CMPIN | 13 | Input of independent comparator. Internal reference, output polarity and deglitch time are selectable by SMBus. Place a resistor between CMPIN and CMPOUT to program hysteresis when the polarity is HIGH. If comparator is not in use, CMPIN is tied to ground, and CMPOUT is left floating. |
| CMPOUT | 14 | Open-drain output of independent comparator. Place 10-kΩ pull-up resistor from CMPOUT to pull-up supply rail. Comparator reference, output polarity and deglitch time are selectable by SMBus. The comparator is active when REGN is available. If comparator is not in use, CMPIN is tied to ground, and CMPOUT is left floating. |
| BATPRES | 15 | Active low battery present input signal. Low indicates battery present, high indicates battery absent. The device exits the LEARN function and turns on ACFET/RBFET if BATPRES pin is pulled HIGH. Note that ACFET/RBFET is not driven on until BATFET has been turned off in order to protect against adapter to battery short. Upon BATPRES from LOW to HIGH, battery charging and hybrid power boost mode are disabled. The host can enable charging and hybrid power boost mode by write to REG0x14() and REG0x15() when BATPRES is HIGH. |
| BST_STAT | 16 | Active low, open-drain output for hybrid power boost mode indication. It is pulled low when the IC is operating in either hybrid boost mode or battery only boost mode. Otherwise, it is pulled HIGH. Connect a 10-kΩ pull-up resistor from BST_STAT pin to the pull-up supply rail. |
| BATSRC | 17 | Connect to the source of N-channel BATFET. BATDRV voltage is 6 V above BATSRC to turn on BATFET. Place a 10-Ω resistor from BATSRC to the source of BATFET to limit the inrush current on BATSRC pin. |
| BATDRV | 18 | Charge pump output to drive N-channel MOSFET between battery and system (BATFET). BATDRV voltage is 6 V above BATSRC to turn on BATFET and power system from battery. BATDRV is shorted to BATSRC to turn off BATFET. Place a 4-kΩ resistor from BATDRV to the gate of BATFET to limit the inrush current on BATDRV pin. |
| SRN | 19 | Charge current sense resistor negative input. SRN pin is for battery voltage sensing as well. Connect SRN pin with a 0.1-μF ceramic capacitor to GND for common-mode filtering. Connect a 0.1-μF ceramic capacitor from SRP to SRN to provide differential mode filtering. Place a 10-Ω resistor at the SRN pin to protect against reverse-polarity battery insertion. |
| SRP | 20 | Charge current sense resistor positive input. Connect SRP pin with a 0.1-μF ceramic capacitor to GND for common-mode filtering. Connect a 0.1-μF ceramic capacitor from SRP to SRN to provide differential mode filtering. Place a 10-Ω resistor at the SRP pin to protect against reverse-polarity battery insertion. |
| ILIM | 21 | Charge current and discharge current limit. VILIM = 20 × (VSRP – VSRN) for charge current and VILIM = 5 × (VSRN – VSRP) for discharge current. Program ILIM voltage by connecting a resistor divider from system reference 3.3-V rail to ILIM pin to GND pin. The lower of ILIM voltage and 0x14() (for charge) or 0x39 (for discharge) reference sets actual regulation limit. Charging and Hybrid Boost are disabled if ILIM is pulled below 90 mV. |
| GND | 22 | IC ground. On PCB layout, connect to analog ground plane, and only connect to power ground plane through pad underneath IC. |
| LODRV | 23 | Low-side power MOSFET driver output. Connect to low-side N-channel MOSFET gate. |
| REGN | 24 | 6-V linear regulator output supplied from VCC. The LDO is active when ACDET above 0.6 V, VCC above UVLO. Connect a ≥ 2.2-μF 0603 ceramic capacitor from REGN to GND. The diode between REGN and BTST is integrated. |
| BTST | 25 | High-side power MOSFET driver power supply. Connect a 47-nF capacitor from BTST to PHASE. The diode between REGN and BTST is integrated inside the IC. |
| HIDRV | 26 | High-side power MOSFET driver output. Connect to the high side N-channel MOSFET gate. |
| PHASE | 27 | High-side power MOSFET driver source. Connect to the source of the high-side N-channel MOSFET. |
| VCC | 28 | Input supply to power the IC. Use 10-Ω resistor and 1-μF capacitor to ground as a low pass filter to limit inrush current. A diode OR is connected to VCC. It powers te charger IC from input adapter or system rail if battery only boost mode is supported. The diode OR instead powers the charger IC from adapter or battery rail if battery only boost mode is not supported. Refer to Section 7 for examples with and without battery only boost support. |
| Thermal Pad | – | Exposed pad beneath the IC. Analog ground and power ground star-connected only at the thermal pad plane. Always solder the thermal pad to the board and have vias on the thermal pad plane connecting to analog ground and power ground planes. It also serves as a thermal pad to dissipate heat. |