ZHCSFU8B May 2016 – December 2021 ADC32RF80 , ADC32RF83
PRODUCTION DATA
When the offset corrector is bypassed, offset mismatch among interleaving ADC cores appears in the ADC output spectrum. To correct the effects of mismatch, place the ADC in an idle channel state (no signal at the ADC inputs) and the corrector must be allowed to run for some time to estimate the mismatch, then the corrector is frozen so that the last estimated value is held. Required register writes are provided in Table 9-4.
| STEP | REGISTER WRITE | COMMENT |
|---|---|---|
| STEPS FOR FREEZING THE CORRECTOR BLOCK | ||
| 1 | — | Signal source is turned off. The device detects an idle channel at its input. |
| 2 | — | Wait for at least 0.4 ms for the corrector to estimate the internal offset |
| 3 | Address 4001h, value 00h | Select Offset Corr Page Channel A |
| Address 4002h, value 00h | ||
| Address 4003h, value 00h | ||
| Address 4004h, value 61h | ||
| Address 6068h, value C2h | Freeze the corrector for channel A | |
| Address 4003h, value 01h | Select Offset Corr Page Channel B | |
| Address 6068h, value C2h | Freeze the corrector for channel B | |
| 4 | — | Signal source can now be turned on |
| STEPS FOR BYPASSING THE CORRECTOR BLOCK | ||
| 1 | Address 4001h, value 00h | — |
| Address 4002h, value 00h | ||
| Address 4003h, value 00h | ||
| Address 4004h, value 61h | Select Offset Corr Page Channel A | |
| Address 6068h, value 46h | Disable the corrector for channel A | |
| Address 4003h, value 01h | Select Offset Corr Page Channel B | |
| Address 6068h, value 46h | Disable the corrector for channel B | |