日产又大又黄又爽又猛,高清免费在线观看中文字幕av,最新在线伦费观看中文

ZHCSFU8B May 2016 – December 2021 ADC32RF80 , ADC32RF83

PRODUCTION DATA

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

RMP|72
- MPQF396A
RRH|72
- MPQF526

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

8.3.8.2 Crossing Detector

In this detector mode the peak is computed over eight samples of the ADC output. Next, the peak for a block of N samples (N × S`) is computed over a programmable block length and then the peak is compared against two sets of programmable thresholds (with hysteresis). The crossing detector counts how many f_S / 8 clock cycles that the block detector outputs are set high over a programmable time period and compares the counter value against the programmable thresholds. The alarm outputs are updated at the end of the time period, routed to the GPIO pins, and held in that state through the next cycle, as shown in Figure 8-48 and Figure 8-49. Alternatively, a 2-bit format can be used but (because the ADC32RF8x has four GPIO pins available) this feature uses all four pins for a single channel.

Figure 8-48 Crossing Detector Implementation

Figure 8-49 Crossing Detector Timing Diagram

Table 8-10 shows the register configurations required to set up the crossing detector. The detector operates in the
f_S / 8 clock domain. The AGC modes can be configured separately for channel A (54xxh) and channel B (5Cxxh), although some registers are common in 54xxh (such as the GPIO pin selection).

Table 8-10 Registers Required for the Crossing Detector Operation

REGISTER	ADDRESS	DESCRIPTION
PKDET EN	5400h, 5C00h	Enables peak detector
BLKPKDET	5401h, 5402h, 5403h, 5C01h, 5C02h, 5C03h	Sets the block length N of number of samples (S`). Number of actual ADC samples is 8x this value: N is 17 bits: 1 to 2¹⁶.
BLKTHHH, BLKTHHL, BLKTHLH, BLKTHLL	5407h, 5408h, 5409h, 540Ah, 5C07h, 5C08h, 5C09h, 5C0Ah	Sets the different thresholds for the hysteresis function values from 0 to 256 (where 256 is equivalent to the peak amplitude). For example: if BLKTHHH is to –2 dBFS from peak, 10^{(–2 / 20)} × 256 = 203, then set 5407h and 5C07h = CBh.
FILT0LPSEL	540Dh, 5C0Dh	Select block detector output or 2-bit output mode as the input to the interrupt identification register (IIR) filter.
TIMECONST	540Eh, 540Fh, 5C0Eh, 5C0Fh	Sets the crossing detector time period for N = 0 to 15 as 2N × f_S / 8 clock cycles. The maximum time period is 32768 × f_S / 8 clock cycles (approximately 87 μs at 3 GSPS).
FIL0THH, FIL0THL, FIL1THH, FIL1THL	540Fh-5412h, 5C0Fh-5C12h, 5416h-5419h, 5C16h-5C19h	Comparison thresholds for the crossing detector counter. These thresholds are 16-bit thresholds in 2.14-signed notation. A value of 1 (4000h) corresponds to 100% crossings, a value of 0.125 (0800h) corresponds to 12.5% crossings.
DWELLIIR	541Dh, 541Eh, 5C1Dh, 5C1Eh	DWELL counter for the IIR filter hysteresis.
IIR0 2BIT EN, IIR1 2BIT EN	5413h, 54114h, 5C13h, 5C114h	Enables 2-bit output format for the crossing detector.
OUTSEL GPIO[4:1]	5432h, 5433h, 5434h, 5435h	Connects the IIRPKDET0, IIRPKDET1 alarms to the GPIO pins; common register.
IODIR	5437h	Selects the direction for the four GPIO pins; common register.
RESET AGC	542Bh, 5C2Bh	After configuration, reset the AGC module to start operation.