The switching node rise and fall times must be minimized for minimum switching loss. Proper layout of the components to minimize high frequency current path loop is important to prevent electrical and magnetic field radiation and high frequency resonant problems. Follow this specific order carefully to achieve the proper layout.

1. Place high frequency decoupling capacitors for VIN and SYS as close possible to their respective pins and ground pin on the same layer as the charger IC (in other words, no vias) in order to have the smallest current return loop.
2. Place the REGN capacitor to ground and BTST capacitors to SW as close as possible to their respective pins.
3. Place high frequency decoupling capacitors for current sensing resistors as close as possible to their respective pins. Route the traces from the sense resistors to their IC away from the power pins (VIN, SWx, SYS).
4. Place the inductor as near to the SW1 and SW2 pins as possible given step 1 above. It is acceptable to use multiple vias to make these connections as the vias are only adding small amounts of inductance and resistance to an inductor with much higher inductance and DCR.
5. While this EVM has analog ground (AGND) and power ground (PGND) planes that connect close to the charge GND pin, two grounds planes/pours are not required. Resistors and capacitors used for setting sensitive nodes (for example, ACx, SRx, ILIM_HIZ, TS) can use one common ground plane but with their ground terminals connected away from high current ground return paths containing switching noise

See the EVM design for the recommended component placement with trace and via locations.