Use the following steps for reverse/OTG/source mode verification:

1. Turn off and disconnect PS #1.
2. Set Load #1, the battery simulator, to 7V and 2A current limit.
   Note: If Load #1 connected from J3 BAT to GND is not a four quadrant supply, then remove Load #1 and use PS #1, replace with 7V, 2 A current limit.
3. In the EVM software on the 16-bit tab, confirm that VIN_REV, the reverse mode regulation voltage, is set to 5000 mV and IIN_REV, the reverse mode output current limit, is set to 1000 mA.
4. In the EVM software in the 8 Bit Chip Single-bit section
   1. Uncheck EN_BAT_DETECT
   2. Check EN_REV
5. Connect disabled Load #2 across J2 VPWR and PGND
6. Set Load #2 to 500 mA constant current load and the turn on the load.
7. To confirm the reverse regulation,
   • Measure→ V_BUS = 5000 mV + 155 mV
8. Turn off and disconnect the power supply.
9. Remove Load #2 from the connection.