Proper PCB layout is extremely important in a
high-current, fast-switching circuit to provide
appropriate device operation and design robustness.
The UCC5714x-Q1 gate
driver incorporates short propagation delays and
powerful output stages capable of delivering large
current peaks with very fast rise and fall times at
the gate of power switch to facilitate voltage
transitions very quickly. Very high di/dt can cause
unacceptable ringing if the trace lengths and
impedances are not well controlled. The following
circuit layout guidelines are recommended when
designing with these high-speed drivers.
- Place the driver device as close as possible to
power device to minimize the length of
high-current traces between the driver output pins
and the gate of the power switch device.
- Place the bypass capacitors between VDD pin and the COM pin as close to the driver pins
as possible to minimize trace length for improved noise filtering. TI recommends having
two capacitors; a 100nF ceramic surface-mount capacitor placed less than 1mm from the
VDD pin of the device and another ceramic surface-mount capacitor of few microfarads
added in parallel. These capacitors support high peak current being drawn from VDD
during turnon of power switch. The use of low inductance surface-mount components such
as chip capacitors is highly recommended.
- The turnon and turn-off current loop paths
(driver device, power switch and VDD bypass
capacitor) should be minimized as much as possible
in order to keep the stray inductance to a
minimum. High di/dt is established in these loops
at two instances – during turnon and turn-off
transients, which induces significant voltage
transients on the output pins of the driver device
and gate of the power switch.
- Wherever possible, parallel the source and return
traces of a current loop, taking advantage of flux
cancellation
- Separate power traces and signal traces, such as
output and input signals.
- To minimize switch node transients and ringing,
adding some gate resistance and/or snubbers on the
power devices may be necessary. These measures may
also reduce EMI.
- Star-point grounding is a good way to minimize noise coupling from one current loop to
another. The COM of the driver should be connected to the other circuit nodes such as
source of power switch, ground of PWM controller, and so forth, at a single point. The
connected paths should be as short as possible to reduce inductance and be as wide as
possible to reduce resistance.
- Use a ground plane to provide noise shielding.
Fast rise and fall times at OUT pin may corrupt
the input signals during transitions. The ground
plane must not be a conduction path for any
current loop. Instead the ground plane should be
connected to the star-point with one trace to
establish the ground potential. In addition to
noise shielding, the ground plane can help in
power dissipation as well.
- Place OCP filter capacitor to the driver OCP pin as close as possible. Also minimize
the current sense loop will help with noise immunity. The sense resisitor should be
placeed close to the IGBT emmiter or source of the MOSFET to decrease the parasitic
inductance. A low ESL film resistor is recommened for sense resistor.