ZHCSON5 april 2023 UCC21756-Q1
PRODUCTION DATA
Figure 5-1 UCC21756-Q1
DW SOIC (16)Top
View| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| AIN | 1 | I | Isolated analog sensing input, parallel a small capacitor to COM for better noise immunity. Tie to COM if unused. |
| DESAT | 2 | I | Desaturation current protection input. Tie to COM if unused. |
| COM | 3 | P | Common ground reference, connecting to emitter pin for IGBT and source pin for SiC-MOSFET |
| OUTH | 4 | O | Gate driver output pullup |
| VDD | 5 | P | Positive supply rail for gate drive voltage. Bypass with a >10-μF capacitor to COM to support specified gate driver source peak current capability. Place decoupling capacitor close to the pin. |
| OUTL | 6 | O | Gate driver output pulldown |
| CLMPI | 7 | I | Internal Active Miller clamp, connecting this pin directly to the gate of the power transistor. Leave floating or tie to VEE if unused. |
| VEE | 8 | P | Negative supply rail for gate drive voltage. Bypass with a >10-μF capacitor to COM to support specified gate driver sink peak current capability. Place decoupling capacitor close to the pin. |
| GND | 9 | P | Input power supply and logic ground reference |
| IN+ | 10 | I | Non-inverting gate driver control input. Tie to VCC if unused. |
| IN– | 11 | I | Inverting gate driver control input. Tie to GND if unused. |
| RDY | 12 | O | Power good for VCC-GND and VDD-COM. RDY is open-drain configuration and can be paralleled with other RDY signals. |
| FLT | 13 | O | Active low fault alarm output upon overcurrent or short circuit. FLT is in open-drain configuration and can be paralleled with other faults. |
| RST/EN | 14 | I | The RST/EN serves two purposes: 1) Enables or shuts down the output side. The FET is turned off by a regular turn-off, if pin EN is set to low; 2) Resets the DESAT condition signaled on the FLT pin if the pin RST/EN is set to low for more than 1000 ns. A reset of signal FLT is asserted at the rising edge of pin RST/EN. For automatic RESET function, this pin only serves as an EN pin. Enable or shutdown the output side. The FET is turned off by a regular turn-off, if pin EN is set to low. Tie to IN+ for automatic reset. |
| VCC | 15 | P | Input power supply from 3 V to 5.5 V. Bypass with a >1-μF capacitor to GND. Place decoupling capacitor close to the pin. |
| APWM | 16 | O | Isolated analog sensing PWM output. Leave floating if unused. |