ZHCSMM7A April 2022 – May 2024 TUSB1004
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| I2C | ||||||
| fSCL | I2C clock frequency | 1 | MHz | |||
| tBUF | Bus free time between START and STOP conditions | Refer to Figure 5-2 | 0.5 | μs | ||
| tHD_STA | Hold time after repeated START condition. After this period, the first clock pulse is generated | Refer to Figure 5-2 | 0.26 | μs | ||
| tLOW | Low period of the I2C clock | Refer to Figure 5-2 | 0.5 | μs | ||
| tHIGH | High period of the I2C clock | Refer to Figure 5-2 | 0.26 | μs | ||
| tSU_STA | Setup time for a repeated START condition | Refer to Figure 5-2 | 0.26 | μs | ||
| tHD_DAT | Data hold time | Refer to Figure 5-2 | 0 | μs | ||
| tSU_DAT | Data setup time | Refer to Figure 5-2 | 50 | ns | ||
| tR | Rise time of both SDA and SCL signals | Refer to Figure 5-2 | 120 | ns | ||
| tF | Fall time of both SDA and SCL signals | Refer to Figure 5-2 | 20 × (V(I2C)/5.5 V) | 120 | ns | |
| tSU_STO | Setup time for STOP condition | Refer to Figure 5-2 | 0.26 | μs | ||
| Cb | Capacitive load for each bus line | 150 | pF | |||