ZHCSI58C October 2009 – May 2018 TPS65720 , TPS65721
PRODUCTION DATA.
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| RESET and PB_IN | ||||||
| TRESET | Reset delay time on pin RESET | Low to high transition of RESET pin, Bit RESET_DELAY = 0 | 9 | 11 | 13 | ms |
| Low to high transition of RESET pin, Bit RESET_DELAY = 1 | 70 | 90 | 110 | |||
| HIGH to LOW transition of RESET pin RESET will go low by HOLD pin going LOW AND HOLD Bit set to 0 OR voltage at Vreset falling below the threshold | 10 | μs | ||||
| Tdebounce | Debounce time at PB_IN | Rising and falling voltage | 39 | 50 | 60 | ms |
| POWER OUTPUTS, DCDC1 and LDO1 | ||||||
| tStart | DCDC1 Start-up time | Time from active EN to Start switching | 170 | μs | ||
| tRamp | DCDC1 VOUT ramp time | Time to ramp from 5% to 95% of VOUT | 250 | μs | ||
| LDO1 PGOOD debounce time | Internal PGOOD comparator at VOUTLDO1 is debounced by | 80 | μs | |||
| tRamp | LDO1 VOUT Ramp time | Internal soft-start when LDO is enabled;
Time to ramp from 5% to 95% of VOUT |
250 | μs | ||
| POWER PATH | ||||||
| tDGL(PGOOD) | Deglitch time, input power detected status | Time measured from VIN: 0 V → 5 V 1 μs
rise time to PGOOD = LO |
2 | ms | ||
| tBLK(OVP) | Input overvoltage blanking time | 50 | μs | |||
| tREC(OVP) | Input overvoltage recovery time | Time measured from VAC: 11 V → 5 V 1 μs
fall time to <CH_PGOOD> = 0 |
2 | ms | ||
| tDGL(SC2) | Output short-circuit detection deglitch time, supplement mode short circuit
VBAT – VOUT > VO(SC2) indicates short-circuit |
250 | μs | |||
| tREC(SC2) | Recovery time, supplement mode short circuit | 60 | ms | |||
| CHARGER | ||||||
| tDGL1(LOWV) | Deglitch time on pre-charge to fast-charge transition | 25 | ms | |||
| tDGL2(LOWV) | Deglitch time on fast-charge to pre-charge transition | 25 | ms | |||
| tDGL(TERM) | Deglitch time, termination detected | 25 | ms | |||
| tDGL(RCH) | Deglitch time, recharge threshold detected | 62.5 | ms | |||
| tDGL(NO-IN) | Delay time, input power loss to charger turn-off | VBAT = 3.6 V. Time measured from VIN: 5 V → 3.3 V 1 μs fall time | 20 | ms | ||
| tDET | Battery detection timer | 250 | ms | |||
| BATTERY PACK MONITOR | ||||||
| tDGL(TS) | Deglitch time, pack temperature fault detection | 50 | ms | |||
| tSW(VBAT-TS) | MUX switching time | Bit <OPAMP+MUX> toggles | 1 | ms | ||
| I2C COMMUNICATION | ||||||
| fMAX | Clock frequency | 400 | kHz | |||
| twH(HIGH) | Clock high time | 600 | ns | |||
| twL(LOW) | Clock low time | 1300 | ns | |||
| tR | DATA and CLK rise time | 300 | ns | |||
| tF | DATA and CLK fall time | 300 | ns | |||
| th(STA) | Hold time (repeated) START condition (after this period the first clock pulse is generated) | 600 | ns | |||
| th(DATA) | Setup time for repeated START condition | 600 | ns | |||
| th(DATA) | Data input hold time | 0 | ns | |||
| tsu(DATA) | Data input setup time | 100 | ns | |||
| tsu(STO) | STOP condition setup time | 600 | ns | |||
| t(BUF) | Bus free time | 1300 | ns | |||