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ZHCSOS1 March 2022 TPS629210E

PRODUCTION DATA

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

DRL|8
- MPCS002F

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

zhcsos1_oa

7.5 Electrical Characteristics

V_IN = 3 V to 17 V, T_J = –55°C to +150°C, typical values at V_I = 12 V and T_A = 25°C,unless otherwise noted

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY
I_Q	Operating quiescent current (power save mode)	I_OUT = 0 mA, device not switching		4		μA
I_Q;PWM	Operating quiescent current (PWM mode)	V_IN = 12 V, V_OUT = 1.2 V; I_OUT = 0 mA, device switching		5		mA
I_SD	Shutdown current into the VIN pin	EN = 0 V		0.25	3	μA
V_UVLO	Undervoltage lockout	V_IN rising	2.85	2.95	3.0	V
V_UVLO	Undervoltage lockout	V_IN falling	2.65	2.75	2.85	V
V_UVLO	Undervoltage lockout hysteresis			200		mV
CONTROL AND INTERFACE
I_LKG	EN input leakage current	EN = V_IN		3	300	nA
V_IH;MODE	High-level input voltage at the MODE/S-CONF pin		1.0			V
V_IL;MODE	Low-level input voltage at the MODE/S-CONF pin				0.15	V
V_IH	High-level input voltage at the EN pin		0.97	1.0	1.03	V
V_IL	Low-level input voltage at the EN pin		0.87	0.9	0.93	V
V_PG	Power-good threshold	V_FB rising, referenced to V_FB nominal	93%	96%	99%
V_PG	Power-good threshold	V_FB falling, referenced to V_FB nominal	89%	93%	96%
V_{PG_HYS}	Power-good threshold hysteresis	Hysteresis		3%
t_PG,DLY	Power-good delay time			32		μs
t_PG,DLY	Power-good pulldown resistance			10		?
V_PG,OL	Low-level output voltage at the PG pin	I_SINK = 1 mA			0.1	V
I_PG,LKG	Input leakage current into the PG pin	V_PG = 5 V		0.01	1	μA
POWER SWITCHES
R_DS;ON	High-side FET on resistance			250		mΩ
R_DS;ON	Low-side FET on resistance			85		mΩ
I_LIM	High-side FET current limit		1.5	1.8	2.1	A
I_LIM	Low-side FET current limit		1.3	1.6	1.9	A
I_LIM;SINK	Low-side FET sink current limit		0.8	1	1.2	A
T_SD	Thermal shutdown threshold	T_J rising		170		°C
T_SD	Thermal shutdown hysteresis	T_J falling		20		°C
f_SW	Switching frequency	2.5-MHz selection (FPWM mode)		2.5		MHz
f_SW	Switching frequency	1.0-MHz selection (FPWM mode)		1.0		MHz
T_ON(MIN)	Minimum on time			40		ns
I_LKG;SW	Leakage current into the SW pin	EN = 0 V, V_SW = V_OS = 5.5 V		0.1	5	μA
OUTPUT
V_O	Output voltage regulation	VSET configuration selected, T_J = 25°C	–0.75%		+0.75%
V_O	Output voltage regulation	VSET option selected, –55°C ≤ T_J ≤ 150°C	–1.5%		+1%
V_FB	Feedback regulation voltage	Adjustable configuration selected		0.6		V
V_FB	Feedback voltage regulation	FB option selected, T_J = 25°C	–0.5 %		+ 0.5%
V_FB	Feedback voltage regulation	FB option selected, –55°C ≤ T_J ≤ 150°C	–1.5%		+0.5%
I_FB	Input leakage current into the FB pin	Adjustable configuration, V_FB = 0.6 V		1	100	nA
T_delay	Start-up delay time	I_O = 0 mA, time from EN rising edge until start switching, external FB configuration selected		700	1750	μs
T_delay	Start-up delay time	I_O = 0 mA, time from EN rising edge until start switching, VSET configuration selected		1000	2000	μs
T_SS	Soft-start time	I_O = 0 mA after T_delay, from first switching pulse until target V_O		600	700	μs
R_DISCH	Active discharge resistance	Discharge = ON - option selected, EN = LOW		7.5	20	?