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ZHCSM63C September 2020 – December 2021 TPS542A52

PRODUCTION DATA

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

RJM|33
- MPQF490B

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6.5 Electrical Characteristics

T_J = -40℃ to 150℃ (unless otherwise noted)

PARAMETER (1)		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT SUPPLY (PVIN, AVIN PINS)
V_IN	PVIN and AVIN supply range		4	12	18	V
I_Q	Shutdown current	EN < 0.4 V		17		μA
I_Q	PFM Mode current	V_IN = 12 V, V_OUT = 1 V, EN > 1.2 V, no switching, V_RSP > 5*V_VSET		1800		μA
ENABLE and UVLO (EN PIN)
V_EN	Enable threshold: ON/OFF	Rising and falling		1.2		V
I_EN	Enable input current	Enable threshold – 50 mV		–0.6		μA
I_EN	Enable input current	Enable threshold + 50 mV		–5		μA
UVLO (AVIN, PVIN PINS)
AVIN, PVIN	UVLO rising threshold		3.75	3.85	4	V
	UVLO falling threshold		3.50	3.6	3.7
	Hysteresis			0.25
INTERNAL REGULATOR, POWER STAGE (VREG PIN)
V_VREG	LDO output voltage	LDO output current = 0A	4.3	4.7	4.96	V
V_VREG	LDO output voltage	LDO output current = 30mA		4.7		V
	Output current limit	V_VREG = 4.7V	120	170	220	mA
	Nominal output current	f_sw = 2.2 MHz, output current = 15 A, V_VREG = 4.7V		30		mA
V_REG(UVLO)	UVLO rising yhreshold			2.8		V
	UVLO falling threshold			2.6
	UVLO hysteresis			0.2
CONTROL REFERENCE VOLTAGE (SREF PIN)
V_SREF	SREF output voltage	Tolerance included in RSP/RSN accuracy		1.2		V
ISREF	SREF current sourcing capability	Resistance > 6 kΩ			200	μA
OUTPUT VOLTAGE REGULATION ACCURACY
	Output Voltage Accuracy; Vout = 1V	Total internal accuracy, measured at the RSP and RSN pins = 5*VSET, VSET = 0.2V, –40 to 150°C	-15		15	mV
	Output Voltage Accuracy; Vout =1V	Total internal accuracy, measured at the RSP and RSN pins = 5*VSET, VSET = 0.2V, –40 to 125°C	-13		13	mV
	Output Voltage Accuracy; Vout = 1V	Total internal accuracy, measured at the RSP and RSN pins = 5*VSET, VSET = 0.2V, 0 to 105°C	-11.0		9.0	mV
	Output Voltage Accuracy; Vout = 0.8V	Total internal accuracy, measured at the RSP and RSN pins = 5*VSET, VSET = 0.16V, –40 to 150°C	-15		15	mV
	Output Voltage Accuracy; Vout = 1.2V	Total internal accuracy, measured at the RSP and RSN pins = 5*VSET, VSET = 0.24V, –40 to 150°C	-15		15	mV
	Output Voltage Accuracy; Vout = 5.5V ⁽¹⁾	Total internal accuracy, measured at the RSP and RSN pins = 5*VSET, VSET = 1.1V, –40 to 150°C	-30		30	mV
REMOTE SENSE AMPLIFIER
	Unity gain bandwidth ⁽¹⁾			7		MHz
	Open loop gain ⁽¹⁾			83		dB
	Slew rate ⁽¹⁾			2.5		V/us
	Input common mode range ⁽¹⁾		-0.05		1.1	V
Vos	Input offset voltage (RSA and EA combined offset trim) ⁽¹⁾			0.25		mV
SWITCHING FREQUENCY
FSW_1MHz	Switching frequency 1MHz	R_FSEL = 35.7 k? or Short	900	1000	1100	kHz
FSW_400kHz	Switching frequency 400 kHz	R_FSEL = 7.5 k?	-10		15	%
FSW_600kHz	Switching frequency 600 kHz	R_FSEL = 18.2 k?	-10		15	%
FSW_800kHz	Switching frequency 800 kHz	R_FSEL = 26.1 k?	-10		15	%
FSW_1.2MHz	Switching frequency 1.2 MHz	R_FSEL = 47.5 k?	-9		11	%
FSW_2MHz	Switching frequency 2 MHz	R_FSEL = 61.9 k?	-10		15	%
FSW_2.2MHz	Switching frequency 2.2 MHz	R_FSEL = 78.7 k?	-10		15	%
	Minimum On-Time			12		ns
	Minimum Off-Time			85		ns
SYNC
V_IH(SYNC)	High-level input voltage	EN = High	1.35			V
V_IL(SYNC)	Low-level input voltage				0.8	V
	Sync input minimum pulse width				50	ns
Δf_SYNC	SYNC pin frequency range from f_SW		–10%		15%
V_{IH(SYNC)-PROG}	High-level input voltage to enter programming mode when EN = 0V	EN = Low	1.35			V
POWER STAGE
R_ds(on)1	Main high-side MOSFET on-resistance	V_VREG= 4.7 V, T_J = 25°C		9.1		m?
R_ds(on)2	Main Low-side MOSFET on-resistance	V_VREG = 4.7 V, T_J = 25°C		2.6		m?
Tdt(L-H)	Dead-time between low-side off and high-side on transition	VREG = 4.7V, T_J = 25°C		10		ns
Tdt(H-L)	Dead-time between high-side off and low-side on transition	VREG = 4.7V, T_J = 25°C		10		ns
CURRENT SENSE AND PROTECTION
IS1	OC limit HS FET			20		A
IS2	OC limit LS FET 6	R_ILIM = 61.9 k?	17.60	20	22	A
	OC limit LS FET 5	R_ILIM = 47.5 k?	14.78	16.5	18.48
	OC limit LS FET 4	R_ILIM = 35.7 k?	11.56	13	15.62
	OC limit LS FET 3	R_ILIM = 26.1 k?	9.26	10.5	13.56
	OC limit LS FET 2	R_ILIM = 18.2 k?	6.96	8	11.60
	OC limit LS FET 1	R_ILIM = 7.5 k?	4.66	5.5	9.60
IS2	Negative OC limit LS FET			-8.5		A
IS2	Zero-cross detection comparator trip point			135		mA
SOFT-START COUNTER
t_SS	SS setting 1: 2.0MHz CLK	V_VSET = 0.1 V to 0.28 V		0.45		ms
	SS setting 2: 1.0MHz CLK	V_VSET = 0.1 V to 0.28 V		0.9
	SS setting 3: 0.5MHz CLK	V_VSET = 0.1 V to 0.28 V		1.8
	SS setting 4: 0.25MHz CLK	V_VSET = 0.1 V to 0.28 V		3.6
INTERNAL BOOTSTRAP SWITCH
	Forward voltage	V_VREG(BOOT), I_F = 10 mA, T_A = 25^°C		0.16	0.3	V
OUTPUT VOLTAGE OVERSHOOT REDUCTION
POWER-ON DELAY
	Power-on delay time	From EN to SS; V_IN > 4 V		500		us
POWER GOOD and OV/UV WARNING
V_RSP	OV warning level	RSP rising (fault)	105	110	115	% 5*V_VSET
	OV warning level	RSP falling (reset)	100	105	109
	UV warning level	RSP falling (fault)	87	90	93.5
	UV warning level	RSP rising (reset)	91	95	99
	PGD delay time	Delay from SS finish to PGD high		500		μs
R_ds(on)PGDFET		PGD FET On Resistance, I_PGOOD=5mA	4.1	5.8	9.1	?
OUTPUT OVERVOLTAGE PROTECTION (OVP)
V_RSP	OVP trip level	RSP rising (fault), V_VSET ≤ 1.04 V	110	115	120	% 5*V_VSET
V_RSP	OVP reset level	RSP falling	76	80	84	% 5*V_VSET
	OVP delay			100		ns
OUPUT UNDERVOLTAGE PROTECTION (UVP)
V_RSP	UVP detect voltage		76	80	84	% 5*V_SET
	UV delay			100		ns
THERMAL SHUTDOWN
T_SDN	Shutdown temperature⁽¹⁾		155	165		⁰C
	Hysteresis⁽¹⁾			15		⁰C

(1) Specified by design. Not production tested.