ZHCSK92E September 2019 – March 2022 TPS25840-Q1 , TPS25842-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SOFT START | ||||||
| TSS | Internal soft-start time | The time of internal reference to increase from 0 V to 1.0 V | 3 | 5 | 7 | ms |
| HICCUP MODE | ||||||
| NOC | Number of cycles that LS current limit is tripped to enter Hiccup mode | 128 | Cycles | |||
| TOC | Hiccup retry delay time | 118 | ms | |||
| SW (SW PIN) | ||||||
| TON_MIN | Minimum turnon-time | 105 | ns | |||
| TON_MAX | Maximum turnon-time, HS timeout in dropout | 7.5 | μs | |||
| TOFF_MIN | Minimum turnoff time | 80 | ns | |||
| Dmax | Maximum switch duty cycle | 98 | % | |||
| TIMING RESISTOR AND INTERNAL CLOCK | ||||||
| fSW_RANGE | Switching frequency range using RT mode | 300 | 2300 | kHz | ||
| fSW | Switching frequency | RT = 49.9 kΩ | 360 | 400 | 440 | kHz |
| Switching frequency | RT = 8.87 kΩ | 1953 | 2100 | 2247 | kHz | |
| FSSS | Frequency span of spread spectrum operation | ±6 | % | |||
| NFET DRIVER | ||||||
| tr | VLS_DR rise time | VOUT = 5.1 V, NFET = CSD87502Q2, time from LS_GD 10% to 90% | 1000 | μs | ||
| tf | VLS_DR fall time | VOUT = 5.1 V, NFET = CSD87502Q2, time from LS_GD time 90% to 10% | 100 | μs | ||
| CURRENT LIMIT - EXTERNAL NFET CONNECTED BETWEEN CSN/OUT AND BUS, LS_GD CONNECTED TO FET GATE | ||||||
| tOC_HIC_ON | ON-time during hiccup mode | 2 | ms | |||
| tOC_HIC_OFF | OFF-time during hiccup mode | 263 | ms | |||
| FAULT DUE TO VBUS OC, VBUS OV, DP OV, DM OV | ||||||
| tDEGLA | Asserting deglitch time | 5.5 | 8.2 | 11.5 | ms | |
| tDEGLD | De-asserting deglitch time | 5.5 | 8.2 | 11.5 | ms | |
| BUCK_ST | ||||||
| tDEGLA | Asserting deglitch time | 88 | 150 | 220 | ms | |
| HIGH-BANDWIDTH ANALOG SWITCH | ||||||
| tpd | Analog switch propagation delay | 0.14 | ns | |||
| tSK | Analog switch skew between opposite transitions of the same port (tPHL – tPLH) | 0.02 | ns | |||
| tOV_Dn | DP_IN and DM_IN overvoltage protection response time | 2 | μs | |||
| tST_DEG_Dn | Deglitch time from Vcc > 4V to DP / DM data switch turn on | 88 | 150 | 220 | ms | |