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ZHCSP87A December 2022 – September 2023 TPS25772-Q1

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RQL|29
- MPQF570A

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

RQL|29
- QFND612

訂購信息

7.16 I2C Requirements and Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature range unless otherwise stated.V_IN = 13.5 V, EN =2 V, unless otherwise stated. V_DD = I2C pullup voltage (3.3 V or 1.8 V)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
I2C_IRQ1s, I2C_IRQ2
I2C_IRQ1m
SDA and SCL Characteristics (Standard, Fast, Fast-mode Plus)
V_IL	Input low signal			0.54	V
V_IH	Input high signal		1.3		V
V_DD = 3.3 V INPUT LOGIC THRESHOLDS
V_IL	Input low signal			0.9	V
V_IH	Input high signal		2.31		V
V_HYS	Input hysteresis		0.165		V
V_OL	Output low voltage	V_DD = 1.8V, I_OL=2 mA		0.36
V_OL	Output low voltage	V_DD = 3.3V, I_OL=3 mA		0.4	V
I_OL	Max output low current	V_OL=0.4 V	12		mA
I_LEAK	Input leakage current	Voltage on pin = 3.3V	–5	5	μA
C_I	pin capacitance (internal)			10	pF
C_b	Capacitive load for each bus line (external). Applies in Standard-mode and Fast-mode.			400	pF
C_b	Capacitive load for each bus line (external). Applies in Fast-mode Plus.			550	pF
COMMON TIMING
t_SP	I2C pulse width suppressed			50	ns
SDA and SCL Characteristics (Standard Mode)
f_SCLS	Clock frequency (slave)	V_DD = 1.8V or 3.3V		100	kHz
t_HD;STA	Start or repeated start condition hold time	V_DD = 1.8V or 3.3V	4		μs
t_LOW	SCL Clock low time	V_DD = 1.8V or 3.3V	4.7		μs
t_HIGH	SCL Clock high time	V_DD = 1.8V or 3.3V	4		μs
t_SU;STA	Start or repeated start condition setup time	V_DD = 1.8V or 3.3V	4.7		μs
t_HD;DAT	Serial data hold time ⁽¹⁾	V_DD = 1.8V or 3.3V	0 ⁽²⁾	- ⁽³⁾	ns
t_SU;DAT	Serial data setup time	V_DD = 1.8V or 3.3V	250		ns
t_r	Rise time of SCL and SDA signals	V_DD = 1.8V or 3.3V; R_PU = 2.8 k?; Cb = 400pF; measure 0.3 × V_DD to 0.7 × V_DD		1000	ns
t_of	Output fall time from V_IH(MIN) to V_IL(MAX)	V_DD = 1.8V or 3.3V; measure 0.3 × V_DD to 0.7 × V_DD		250 ⁽⁴⁾	ns
t_f	Fall time of SCL and SDA signals ⁽²⁾ ⁽⁴⁾ ⁽⁵⁾	V_DD = 1.8V, R_PU = 2.8 k?; 10 pF ≤ C_b ≤ 400 pF		300	ns
t_f	Fall time of SCL and SDA signals ⁽²⁾ ⁽⁴⁾ ⁽⁵⁾	V_DD = 3.3V, R_PU = 2.8 k?; 10 pF ≤ C_b ≤ 400 pF		300	ns
t_SU;STO	Stop condition setup time	V_DD = 1.8V or 3.3V	4		μs
t_BUF	Bus free time between stop and start	V_DD = 1.8V or 3.3V	4.7		μs
t_VD;DAT	Valid data time ⁽⁶⁾	Transmitting Data; V_DD = 1.8V or 3.3V, SCL low to SDA output valid		3.45 ⁽³⁾	μs
t_VD;ACK	Valid data time of ACK condition	Transmitting Data; V_DD = 1.8V or 3.3V, ACK signal from SCL low to SDA valid		3.45 ⁽³⁾	μs
SDA and SCL Characteristics (Fast Mode)
f_SCLS	Clock frequency (slave)	V_DD = 1.8V or 3.3V		400	kHz
t_HD;STA	Start or repeated start condition hold time	V_DD = 1.8V or 3.3V	0.6		μs
t_LOW	SCL Clock low time	V_DD = 1.8V or 3.3V	1.3		μs
t_HIGH	SCL Clock high time	V_DD = 1.8V or 3.3V	0.6		μs
t_SU;STA	Start or repeated start condition setup time	V_DD = 1.8V or 3.3V	0.6		μs
t_HD;DAT	Serial data hold time ⁽¹⁾	V_DD = 1.8V or 3.3V	0 ⁽²⁾	- ⁽³⁾	ns
t_SU;DAT	Serial data setup time	V_DD = 1.8V or 3.3V	100 ⁽⁷⁾		ns
t_r	Rise time of SCL and SDA signals	V_DD = 1.8V or 3.3V; R_PU = 850 ?; C_b = 400 pF; measure 0.3 × V_DD to 0.7 × V_DD	20	300	ns
t_of	Output fall time from V_IH(MIN) to V_IL(MAX)	V_DD = 1.8V; measure 0.3 × V_DD to 0.7 × V_DD	6.55	250 ⁽⁴⁾	ns
t_of	Output fall time from V_IH(MIN) to V_IL(MAX)	V_DD = 3.3V; measure 0.3 × V_DD to 0.7 × V_DD	12	250 ⁽⁴⁾	ns
t_f	Fall time of SCL and SDA signals ⁽²⁾ ⁽⁴⁾ ⁽⁵⁾	V_DD = 1.8V; R_PU = 850 ?; 10 pF ≤ C_b ≤ 400 pF	6.55	300	ns
t_f	Fall time of SCL and SDA signals ⁽²⁾ ⁽⁴⁾ ⁽⁵⁾	V_DD = 3.3V; R_PU = 850 ?; 10 pF ≤ C_b ≤ 400 pF	12	300	ns
t_SU;STO	Stop condition setup time	V_DD = 1.8V or 3.3V	0.6		μs
t_BUF	Bus free time between stop and start	V_DD = 1.8V or 3.3V	1.3		μs
t_VD;DAT	Valid data time ⁽⁶⁾	Transmitting Data; V_DD = 1.8V or 3.3V, SCL low to SDA output valid		0.9 ⁽³⁾	μs
t_VD;ACK	Valid data time of ACK condition	Transmitting Data; V_DD = 1.8V or 3.3V, ACK signal from SCL low to SDA (out) low		0.9 ⁽³⁾	μs

(1) t_HD;DAT = the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.

(2) A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V_IH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL.

(3) The maximum t_HD;DAT could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode, but must be less than the maximum t_VD;DAT or t_VD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (t_LOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the setup time before it releases the clock.

(4) The maximum t_f for the SDA and SCL bus lines is stated in these tables as 300 ns is longer than the specified maximum t_of for the output stages (250 ns). This allows series protection resistors (R_S) to be connected between the SDA and SCL pins and the SDA and SCL bus lines without exceeding the maximum specified t_f.

(5) In Fast-mode Plus, fall time is specified the same for both ouput stage and bus timing. If series resistors (R_S) are used, designers should allow for this when considering bus timing.

(6) t_VD;DAT = time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

(7) A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement t_SU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t_r(max) + t_SU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.