ZHCSBP7C October 2013 – December 2018 TPS24750 , TPS24751
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
This active low, open-drain output is intended to interface to downstream dc/dc converters or monitoring circuits. PGb pulls low after the drain-to-source voltage of the internal FET has fallen below 150 mV and a 3.4 ms deglitch delay has elapsed. It goes open drain when VDS exceeds 220 mV. PGb assumes high impedance status after a 3.4 ms deglitch delay once VDS of internal FET rises up, resulting from GATE being pulled to GND at the following conditions:
This pin can be left floating when not used.