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ZHCSBP7C October 2013 – December 2018 TPS24750 , TPS24751

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RUV|36
- MPQF340

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

RUV|36
- QFND458B

訂購(gòu)信息

7.5 Electrical Characteristics

–40°C ≤ T_J ≤ +125°C, V_CC = 12 V, V_EN = 3 V, R_SET = 191 Ω, R_IMON = 5 kΩ, and R_PROG = 50 kΩ to GND. All voltages referenced to GND, unless otherwise noted.

PARAMETER		CONDITIONS	MIN	NOM	MAX	UNIT
VCC
	UVLO threshold, rising		2.20	2.32	2.45	V
	UVLO threshold, falling		2.10	2.22	2.35	V
	UVLO hysteresis⁽¹⁾			0.1		V
	Supply current	Enabled ― I_OUT + I_VCC + I_SENSE	0.5	1	1.4	mA
	Supply current	Disabled⁽¹⁾ ― EN = 0 V, I_OUT + I_VCC + I_SENSE		0.45		mA
OUT
R_ON	On-resistance	1 A ≤ I_OUT ≤ 10 A at T_J = 25°C		3	3.5	mΩ
R_ON	On-resistance	1 A ≤ I_OUT ≤ 10 A at T_J = 125°C		5	6	mΩ
	Input bias current	V_OUT= 12 V	10	16	30	µA
	Diode forward voltage	V_EN = 0 V, I_OUT = –100 mA, V_OUT > V_SENSE		0.8	1	V
	Leakage current - DRAIN to OUT	V_EN= 0 V, V_OUT = 0 V, V_DRAIN = 18 V at 25°C		0	1	µA
	Leakage current - DRAIN to OUT	V_EN = 0 V, V_OUT = 0 V, V_DRAIN = 18 V at 125°C		2	5	µA
C_iss	Input capacitance	V_GS = 0 V, V_DRAIN-OUT = 15 V, f = 1 MHz		2710	3250	pF
C_oss	Output capacitance			635	762	pF
C_rss	Reverse transfer capacitance			48	60	pF
Q_g	Gate charge total (4.5 V)	V_DRAIN-OUT = 15 V, I_OUT = 20 A		17.5	21.5	nC
Qg(th)	Gate charge at Vth	V_DRAIN-OUT = 15 V, I_OUT = 20 A		4.1		nC
EN
	Threshold voltage, falling		1.2	1.3	1.4	V
	Hysteresis⁽¹⁾			50		mV
	Input leakage current	0 V ≤ V_EN ≤ 30 V	–1	0	1	µA
	Turnoff time	EN ↓ to V_GATE < 1 V	3	8	25	µs
	Deglitch time	EN ↑	8	14	21	µs
	Disable delay	EN ↓ to GATE ↓, C_GATE = 0, t_pff50–90, See Figure 28	0.1	0.4	1.8	µs
	Turnon delay	C_OUT = 2.2 uF, V_EN ↑ to V_OUT ↑, V_EN: 0 V to 3 V, V_OUT : 90% V_CC		800		µs
OV
	Threshold voltage, rising		1.25	1.35	1.45	V
	Hysteresis⁽¹⁾			60		mV
	Input leakage current	0 V ≤ V_OV ≤ 30 V	–1	0	1	µA
	Deglitch time	OV rising	0.5	1.2	1.5	µs
FLTb
	Output low voltage	Sinking 2 mA		0.11	0.25	V
	Input leakage current	V_FLTb = 0 V, 30 V	–1	0	1	µA
PGb
	Threshold	V_{(SENSE – OUT)} rising, PGb going high	140	220	340	mV
	Hysteresis⁽¹⁾	Measured V_{(SENSE – OUT)} falling, PGb going low		70		mV
	Output low voltage	Sinking 2 mA		0.11	0.25	V
	Input leakage current	V_PGb = 0 V, 30 V	–1	0	1	µA
	Delay (deglitch) time	Rising or falling edge	2	3.4	6	ms
PROG
	Bias voltage	Sourcing 10 µA	0.65	0.675	0.7	V
	Input leakage current	V_PROG = 1.5 V	–0.2	0	0.2	µA
TIMER
	Sourcing current	V_TIMER = 0 V	8	10	12	µA
	Sinking current	V_TIMER = 2 V	8	10	12	µA
	Sinking current	V_EN = 0 V, V_TIMER = 2 V	2	4.5	7	mA
	Upper threshold voltage		1.3	1.35	1.4	V
	Lower threshold voltage		0.33	0.35	0.37	V
	Timer activation voltage	Raise GATE until I_TIMER sinking, measure V_{(GATE – VCC)}, V_VCC = 12 V	5	5.8	7	V
	Retry duty cycle	During over current and short circuit conditions (TPS24751 only)		4%
IMON
	Circuit breaker threshold		650	675	696	mV
	Input referred offset of servo amplifier	At T_J = 25°C	–1	0	1	mV
	Input referred offset of servo amplifier	T_J from –40°C to +125°C	–1.5	0	1.5	mV
SET
	Input referred offset of servo amplifier	Measure SET to SENSE	–1.5	0	1.5	mV
GATE
	Output voltage	V_OUT = 12 V	23.5	25.7	28	V
	Clamp voltage	Inject 10 µA into GATE, measure V_{(GATE – VCC)}	12	13.9	15.5	V
	Sourcing current	V_GATE = 12 V	20	30	40	µA
	Sinking current	Fast turnoff, V_GATE = 14 V	0.4	1	1.4	A
		Sustained, V_GATE = 4 V to 23 V	6	11	20	mA
		In inrush current limit, V_GATE = 4 V to 23 V	20	30	40	µA
	Pulldown resistance	Thermal shutdown or V_EN = 0 V	14	20	26	kΩ
	Fast turnoff duration		8	13	18	µs
Turnon delay		V_VCC rising to GATE sourcing, t_prr50-50, See Figure 29		100	375	µs
SENSE
	Input bias current	V_SENSE = 12 V, sinking current		30	40	µA
	Current limit threshold	V_OUT = 12 V	22.5	25	27.5	mV
	Power limit threshold	V_DRAIN–OUT = 8 V, R_PROG = 100 kΩ		4		mV
		V_DRAIN–OUT = 8 V, R_PROG = 50 kΩ	6.6	8	9.6
		V_DRAIN–OUT = 5.37 V, R_PROG = 50 kΩ	10	12	14
		V_DRAIN–OUT = 10.3 V, R_PROG = 25 kΩ	10	12.5	15
	Fast-trip threshold		52	60	68	mV
	Fast-turnoff delay⁽¹⁾	V_{(VCC – SENSE)} = 80 mV, C_GATE = 0 pF, t_prf50–50, See Figure 30		200		ns
OTSD
	Threshold, rising	Temperature referenced to PAD1 of the device. See⁽²⁾	130	140		°C
	Hysteresis⁽¹⁾			10		°C

(1) These parameters are provided for reference only and do not constitute part of TI’s published device specifications for purposes of TI’s product warranty.

(2) The temperature difference between PAD1 and PAD2 must be minimized. See the SOA curve Figure 27 and Power-Limited Start-Up section for temperature limited design.