ZHCSNB6A April 2021 – February 2022 TPS23882B
PRODUCTION DATA
The TPS23882B features a 3-wire I2C interface, using SDAI, SDAO, and SCL. Each transmission includes a START condition sent by the controller, followed by the device address (7-bit) with R/W bit, a register address byte, then one or two data bytes and a STOP condition. The recipient sends an acknowledge bit following each byte transmitted. SDAI/SDAO is stable while SCL is high except during a START or STOP condition.
Figure 9-4 and Figure 9-5 show read and write operations through I2C interface, using configuration A or B (see Table 9-24 for more details). The parametric read operation is applicable to ADC conversion results. The TPS23882B features quick access to the latest addressed register through I2C bus. When a STOP bit is received, the register pointer is not automatically reset.
It is also possible to perform a write operation to many TPS23882B devices at the same time. The target address during this broadcast access is 0x7F, as shown in PIN STATUS Register. Depending on which configuration (A or B) is selected, a global write proceeds as following: