ZHCSNB6A April 2021 – February 2022 TPS23882B
PRODUCTION DATA
| Bit | Field | Type | Reset | Description | ||||
|---|---|---|---|---|---|---|---|---|
| 15-0 | SA_15- SA_0 | R/W | 0 | SRAM and Parity Programing Start Address bits:
the value entered into these registers sets the start address location for the SRAM or Parity programming | ||||
SRAM Programming:
Upon power up, it is recommended that the TPS23882B device's SRAM be programmed with the latest version of SRAM code via the I2C to ensure proper operation and IEEE complaint performance. All I2C traffic other than those commands required to program the SRAM should be deferred until after the SRAM programming sequences are completed.
The latest version of firmware and SRAM release notes may be accessed from the TI mySecure Software webpage.
The SRAM Release Notes and ROM Advisory document includes more detailed information regarding any know issues and changes that were associated with each firmware release.
The SRAM programming control must be completed at the lower I2C address (Channels 1-4, A0 = 0). Configuring this registers for the upper I2C device address (Channels 5-8) will not program the SRAM
For systems that include multiple TPS23882B devices, the 0x7F "global" broadcast I2C address may be used to programmed all of the devices at the same time.
The SRAM programming needs to be delayed at least 50ms from the initial power on (VPWR and VDD above UVLO) of the device to allow for the device to complete its internal hardware initialization process
For more detailed instructions on the SRAM programing procedures please refer the How to Load TPS2388x SRAM Code document on TI.com.
0x60h setup for SRAM Programming: Prior to programming/writing the SRAM, the following bits sequence needs to be completed in register 0x60h:
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PROG_SEL | CPU_RST | - | PAR_EN | RAM_EN | PAR_SEL | R/WZ | CLR_PTR |
| 0 → 1 | 0 → 1 | 0 | 0 | 0 | 0 | 1 → 0 | 0 → 1 → 0 |
The same sequence is required to read the SRAM with the exception that the R/WZ bit needs to be set to “1”.
If the device is in “Safe Mode”, the same sequence as above may be used to reprogram the SRAM.
An I2C write to 0x61h following this sequence actively programs the SRAM program memory starting from the address set in registers 0x62h and 63h.
0x60h setup for SRAM Parity Programming: Following the programming of the SRAM program memory, the following bits sequence needs to be completed in register 0x60h in order to configure the device to program the Parity memory:
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PROG_SEL | CPU_RST | - | PAR_EN | RAM_EN | PAR_SEL | R/WZ | CLR_PTR |
| 0 → 1 | 0 → 1 | 0 | 0 | 0 | 0 → 1 | 1 → 0 | 0 → 1 → 0 |
The same sequence is required to read the Parity with the exception that the R/WZ bit needs to be set to “1".
An I2C write to 0x61h following this sequence actively programs the Parity memory starting from the address set in registers 0x62h and 63h.
0x60h setup to run from SRAM Program Memory: Upon completion of programming, the following bits sequence needs to be completed in register 0x60h in order to enable the device to run properly out of SRAM:
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PROG_SEL | CPU_RST | - | PAR_EN | RAM_EN | PAR_SEL | R/WZ | CLR_PTR |
| 1 → 0 | 1 → 0 | 0 | 0 → 1 | 0 → 1 | 1 → 0 | 0 | 0 |
Within 1ms of the completion of the above sequence, the device will complete a compatibility check on the SRAM
If the SRAM load is determined to be “Valid”: Register 0x41h will have a value between 0x01h and 0xFEh, and the device will return to normal operation.
If the SRAM load is determined to be “Invalid”:
? 0x41h will be set to 0xFFh
? The RAM_EN bit will be internally cleared
? The device will operating in “safe mode” until another programming attempt is completed