ZHCSNB6A April 2021 – February 2022 TPS23882B
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3 Feature Description
- 9.4 Device Functional Modes
- 9.5 I2C Programming
- 9.6
Register Maps
- 9.6.1 Complete Register Set
- 9.6.2
Detailed Register Descriptions
- 9.6.2.1 INTERRUPT Register
- 9.6.2.2 INTERRUPT MASK Register
- 9.6.2.3 POWER EVENT Register
- 9.6.2.4 DETECTION EVENT Register
- 9.6.2.5 FAULT EVENT Register
- 9.6.2.6 START/ILIM EVENT Register
- 9.6.2.7 SUPPLY and FAULT EVENT Register
- 9.6.2.8 CHANNEL 1 DISCOVERY Register
- 9.6.2.9 CHANNEL 2 DISCOVERY Register
- 9.6.2.10 CHANNEL 3 DISCOVERY Register
- 9.6.2.11 CHANNEL 4 DISCOVERY Register
- 9.6.2.12 POWER STATUS Register
- 9.6.2.13 PIN STATUS Register
- 9.6.2.14 OPERATING MODE Register
- 9.6.2.15 DISCONNECT ENABLE Register
- 9.6.2.16 DETECT/CLASS ENABLE Register
- 9.6.2.17 Power Priority / 2Pair PCUT Disable Register Name
- 9.6.2.18 TIMING CONFIGURATION Register
- 9.6.2.19 GENERAL MASK Register
- 9.6.2.20 DETECT/CLASS RESTART Register
- 9.6.2.21 POWER ENABLE Register
- 9.6.2.22 RESET Register
- 9.6.2.23 ID Register
- 9.6.2.24 Connection Check and Auto Class Status Register
- 9.6.2.25 2-Pair Police Ch-1 Configuration Register
- 9.6.2.26 2-Pair Police Ch-2 Configuration Register
- 9.6.2.27 2-Pair Police Ch-3 Configuration Register
- 9.6.2.28 2-Pair Police Ch-4 Configuration Register
- 9.6.2.29 Capacitance (Legacy PD) Detection
- 9.6.2.30 Power-on Fault Register
- 9.6.2.31 PORT RE-MAPPING Register
- 9.6.2.32 Channels 1 and 2 Multi Bit Priority Register
- 9.6.2.33 Channels 3 and 4 Multi Bit Priority Register
- 9.6.2.34 Port Power Allocation Register
- 9.6.2.35 TEMPERATURE Register
- 9.6.2.36 INPUT VOLTAGE Register
- 9.6.2.37 CHANNEL 1 CURRENT Register
- 9.6.2.38 CHANNEL 2 CURRENT Register
- 9.6.2.39 CHANNEL 3 CURRENT Register
- 9.6.2.40 CHANNEL 4 CURRENT Register
- 9.6.2.41 CHANNEL 1 VOLTAGE Register
- 9.6.2.42 CHANNEL 2 VOLTAGE Register
- 9.6.2.43 CHANNEL 3 VOLTAGE Register
- 9.6.2.44 CHANNEL 4 VOLTAGE Register
- 9.6.2.45 2x FOLDBACK SELECTION Register
- 93
- 9.6.2.46 FIRMWARE REVISION Register
- 9.6.2.47 I2C WATCHDOG Register
- 9.6.2.48 DEVICE ID Register
- 9.6.2.49 CHANNEL 1 DETECT RESISTANCE Register
- 9.6.2.50 CHANNEL 2 DETECT RESISTANCE Register
- 9.6.2.51 CHANNEL 3 DETECT RESISTANCE Register
- 9.6.2.52 CHANNEL 4 DETECT RESISTANCE Register
- 9.6.2.53 CHANNEL 1 DETECT CAPACITANCE Register
- 9.6.2.54 CHANNEL 2 DETECT CAPACITANCE Register
- 9.6.2.55 CHANNEL 3 DETECT CAPACITANCE Register
- 9.6.2.56 CHANNEL 4 DETECT CAPACITANCE Register
- 9.6.2.57 CHANNEL 1 ASSIGNED CLASS Register
- 9.6.2.58 CHANNEL 2 ASSIGNED CLASS Register
- 9.6.2.59 CHANNEL 3 ASSIGNED CLASS Register
- 9.6.2.60 CHANNEL 4 ASSIGNED CLASS Register
- 9.6.2.61 AUTO CLASS CONTROL Register
- 9.6.2.62 CHANNEL 1 AUTO CLASS POWER Register
- 9.6.2.63 CHANNEL 2 AUTO CLASS POWER Register
- 9.6.2.64 CHANNEL 3 AUTO CLASS POWER Register
- 9.6.2.65 CHANNEL 4 AUTO CLASS POWER Register
- 9.6.2.66 ALTERNATIVE FOLDBACK Register
- 9.6.2.67 SRAM CONTROL Register
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
6 Pin Configuration and Functions
Figure 6-1 RTQ Package with Exposed Thermal Pad56-Pin VQFNTop ViewTable 6-1 Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| A1-4 | 48–51 | I | I2C A1-A4 address lines. These pins are internally pulled up to VDD. |
| AGND | 21 | — | Analog ground. Connect to GND plane and exposed thermal pad. |
| DGND | 46 | — | Digital ground. Connect to GND plane and exposed thermal pad. |
| DRAIN1-8 | 3, 5, 10, 12, 31, 33, 38, 40 | I | Channel 1-8 output voltage monitor |
| GAT1-8 | 1, 7, 8, 14, 29, 35, 36, 42 | O | Channel 1-8 gate drive output |
| INT | 45 | O | Interrupt output. This pin asserts low when a bit in the interrupt register is asserted. This output is open-drain. |
| KSENSA/B | 4, 11 | I | Kelvin point connection for SEN1-4 |
| KSENSC/D | 32, 39 | I | Kelvin point connection for SEN5-8 |
| NC | 15, 16, 18, 19 | O | No connect pins. These pins are internally biased at 1/3 and 2/3 of VPWR in order to control the voltage gradient from VPWR. Leave open. |
| 22, 27, 28 | — | No connect pin. Leave open. | |
| OSS | 56 | I | Channel 1-8 fast shutdown. This pin is internally pulled down to DGND. |
| RESET | 44 | I | Reset input. When asserted low, the TPS23882B is reset. This pin is internally pulled up to VDD. |
| SCL | 53 | I | Serial clock input for I2C bus. |
| SDAI | 54 | I | Serial data input for I2C bus. This pin can be connected to SDAO for non-isolated systems. |
| SDAO | 55 | O | Serial data output for I2C bus. This pin can be connected to SDAI for non-isolated systems. This output is open-drain. |
| AUTO | 52 | I/O | Autonomous mode enable and selection pin |
| SEN1-8 | 2, 6, 9, 13, 30, 34, 37, 41 | I | Channel 1-8 current sense input |
| TEST0-5 | 20, 23, 24, 25, 26, 47 | I/O | Used internally for test purposes only. Leave open. |
| Thermal pad | — | — | The DGND and AGND terminals must be connected to the exposed thermal pad for proper operation. |
| VDD | 43 | — | Digital supply. Bypass with 0.1 μF to DGND pin. |
| VPWR | 17 | — | Analog 54-V positive supply. Bypass with 0.1 μF to AGND pin. |