ZHCSIT9C November 2018 – February 2024 TMUX1104
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
The TMUX1104 has a transmission gate topology, as shown in Figure 7-3. Any mismatch in the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.
Figure 7-3 Transmission Gate TopologyThe TMUX1104 has special charge-injection cancellation circuitry that reduces the source-to-drain charge injection to 1.5pC at VS = 1V as shown in Figure 7-4.
Figure 7-4 Charge Injection vs Source Voltage