ZHCSIT9C November 2018 – February 2024 TMUX1104
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| A0 | 1 | I | Address line 0. Controls the switch configuration as shown in Table 7-1. |
| S1 | 2 | I/O | Source pin 1. Can be an input or output. |
| GND | 3 | P | Ground (0V) reference |
| S3 | 4 | I/O | Source pin 3. Can be an input or output. |
| EN | 5 | I | Active high logic enable. When this pin is low, all switches are turned off. When this pin is high, the A[1:0] logic inputs determine which switch is turned on. |
| VDD | 6 | P | Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1μF to 10μF between VDD and GND. |
| S4 | 7 | I/O | Source pin 4. Can be an input or output. |
| D | 8 | I/O | Drain pin. Can be an input or output. |
| S2 | 9 | I/O | Source pin 2. Can be an input or output. |
| A1 | 10 | I | Address line 1. Controls the switch configuration as shown in Table 7-1. |