ZHCSHO9Q July 2006 – August 2024 TLK2711-SP
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Pin Configuration and Functions
-
5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Thermal Information
- 5.5 TTL Input Electrical Characteristics
- 5.6 Transmitter/Receiver Electrical Characteristics
- 5.7 Reference Clock (TXCLK) Timing Requirements
- 5.8 TTL Output Switching Characteristics
- 5.9 Typical Characteristics
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 Transmit Interface
- 6.3.2 Transmit Data Bus
- 6.3.3 Data Transmission Latency
- 6.3.4 8-Bit/10-Bit Encoder
- 6.3.5 Pseudo-Random Bit Stream (PRBS) Generator
- 6.3.6 Parallel to Serial
- 6.3.7 High-Speed Data Output
- 6.3.8 Receive Interface
- 6.3.9 Receive Data Bus
- 6.3.10 Data Reception Latency
- 6.3.11 Serial to Parallel
- 6.3.12 Comma Detect and 8-Bit/10-Bit Decoding
- 6.3.13 LOS Detection
- 6.3.14 PRBS Verification
- 6.3.15 Reference Clock Input
- 6.3.16 Operating Frequency Range
- 6.3.17 Testability
- 6.3.18 Loopback Testing
- 6.3.19 BIST
- 6.3.20 Power-On Reset
- 6.4 Device Functional Modes
- 7 Application and Implementation
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
5.8 TTL Output Switching Characteristics
over recommended operating conditions (unless otherwise noted)
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| VOH | High-level output voltage | IOH = –2mA, VDD = MIN | 2.1 | 2.3 | V | |
| VOL | Low-level output voltage | IOL = 2mA, VDD = MIN | 0.25 | 0.5 | V | |
| tr(slew) | Slew rate (rising), magnitude of RXCLK, RKLSB, RKMSB, RXD0 to RXD15 | 0.8V to 2V, C = 5pF, see Figure 5-2 | 0.5 | V/ns | ||
| tf(slew) | Slew rate (falling), magnitude of RXCLK, RKLSB, RKMSB, RXD0 to RXD15 | 0.8V to 2V, C = 5pF, see Figure 5-2 | 0.5 | V/ns | ||
| tsu | RXD0 to RXD15, RKMSB, RKLSB setup to ↑ RXCLK | 50% voltage swing, TXCLK = 80MHz, see Figure 5-2(1) | 3 | ns | ||
| 50% voltage swing, TXCLK = 125MHz, see Figure 5-2(1) | 2.5 | |||||
| th | RXD0 to RXD15, RKMSB, RKLSB hold to ↑ RXCLK | 50% voltage swing, TXCLK = 80MHz, see Figure 5-2(1) | 3 | ns | ||
| 50% voltage swing, TXCLK = 125MHz, see Figure 5-2(1) | 2 | |||||
(1) Nonproduction tested parameters.
Figure 5-1 TTL Data Input Valid Levels for AC Measurements
Figure 5-2 TTL Data Output Valid Levels for AC Measurements
Figure 5-3 Differential and Common-Mode Output Voltage
Figure 5-4 Common-Mode Output Voltage Definitions