ZHCSHO9Q July 2006 – August 2024 TLK2711-SP
PRODUCTION DATA
The high-speed data output driver consists of a voltage mode logic (VML) differential pair optimized for a 50-? impedance environment. The magnitude of the differential-pair signal swing is compatible with pseudo emitter coupled logic (PECL) levels when AC coupled. The line can be directly coupled or AC coupled. See Figure 6-7 and Figure 6-8 for termination details. The outputs also provide preemphasis to compensate for AC loss when driving a cable or PCB backplane trace over a long distance (see Figure 6-3). The level of preemphasis is controlled by PRE (see Table 6-2).
Figure 6-3 Output Voltage Under Preemphasis (VTXP to VTXN)| PRE | PREEMPHASIS LEVEL (%) VOD(P), VOD(D)(1) |
|---|---|
| 0 | 5% |
| 1 | 20% |