ZHCSK43A August 2019 – November 2019 TCAN4551-Q1
PRODUCTION DATA.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RSVD | Internal_read_error | Internal_write_error | Internal_error_log_write | Read_fifo_underflow | Read_fifo_empty | Write_fifo_overflow | |
| RO | W1C | W1C | W1C | W1C | W1C | W1C | |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RSVD | SPI_end_error | Invalid_command | Write_overflow | write_underflow | Read_overflow | read_underflow | |
| RO | W1C | W1C | W1C | W1C | W1C | W1C | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RSVD | |||||||
| RO | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD | Write_fifo_available | Read_fifo_available | Internal_access_active | Internal_error_interrupt | SPI_error_interrupt | Interrupt | |
| RO | RO | RO | RO | RO | RO | RO | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:30 | RSVD | RO | 1’b0 | Reserved |
| 29 | Internal_read_error | W1C | 1’b0 | Internal read received an error response |
| 28 | Internal_write_error | W1C | 1’b0 | Internal write received an error response |
| 27 | Internal_error_log_write | W1C | 1’b0 | Entry written to the Internal error log |
| 26 | Read_fifo_underflow | W1C | 1’b0 | Read FIFO underflow after 1 or more read data words returned |
| 25 | Read_fifo_empty | W1C | 1’b0 | Read FIFO empty for first read data word to return |
| 24 | Write_fifo_overflow | W1C | 1’b0 | Write/command FIFO overflow |
| 23:22 | RSVD | RO | 1’b0 | Reserved |
| 21 | SPI_end_error | W1C | 1’b0 | SPI transfer did not end on a byte boundary |
| 20 | Invalid_command | W1C | 1’b0 | Invalid SPI command received |
| 19 | Write_overflow | W1C | 1’b0 | SPI write sequence had continue requests after the data transfer was completed |
| 18 | write_underflow | W1C | 1’b0 | SPI write sequence ended with less data transferred then requested |
| 17 | Read_overflow | W1C | 1’b0 | SPI read sequence had continue requests after the data transfer was completed |
| 16 | read_underflow | W1C | 1’b0 | SPI read sequence ended with less data transferred then requested |
| 15:8 | RSVD | RO | 8’h00 | Reserved |
| 7:6 | RSVD | RO | 1’b0 | Reserved |
| 5 | Write_fifo_available | RO | 1’b0 | write fifo empty entries is greater than or equal to the write_fifo_threshold |
| 4 | Read_fifo_available | RO | 1’b0 | Read fifo entries is greater than or equal to the read_fifo_threshold |
| 3 | Internal_access_active | RO | U | Internal Multiple transfer mode access in progress |
| 2 | Internal_error_interrupt | RO | 1’b0 | Unmasked Internal error set |
| 1 | SPI_error_interrupt | RO | 1’b0 | Unmasked SPI error set |
| 0 | Interrupt | RO | U | Value of interrupt input level (active high) |