ZHCSWM8A June 2024 – December 2024 TCAN1472-Q1
PRODUCTION DATA
| 參數(shù) | 測試條件 | 最小值 | 典型值 | 最大值 | 單位 | |
|---|---|---|---|---|---|---|
| 器件開關(guān)特性 | ||||||
| tPROP(LOOP1) | 總循環(huán)延遲、驅(qū)動器輸入 (TXD) 至接收器輸出 (RXD)、隱性狀態(tài)至顯性狀態(tài) | 請參閱圖 6-4正常模式,VIO = 4.5V 至 5.5V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),CL(RXD) = 15pF (≤ ±1%) | 90 | 145 | ns | |
| 請參閱圖 6-4正常模式,VIO = 3V 至 3.6V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),CL(RXD) = 15pF (≤ ±1%) | 95 | 155 | ns | |||
| 請參閱圖 6-4正常模式,VIO = 2.25V 至 2.75V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),CL(RXD) = 15pF (≤ ±1%) | 110 | 170 | ns | |||
| 請參閱圖 6-4正常模式,VIO = 1.71V 至 1.89V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),CL(RXD) = 15pF (≤ ±1%) | 125 | 190 | ns | |||
| tPROP(LOOP2) | 總環(huán)路延遲,驅(qū)動器輸入 (TXD) 到接收器輸出 (RXD),顯性狀態(tài)到隱性狀態(tài) | 請參閱圖 6-4正常模式,VIO = 4.5V 至 5.5V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),CL(RXD) = 15pF (≤ ±1%) | 95 | 150 | ns | |
| 請參閱圖 6-4正常模式,VIO = 3V 至 3.6V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),CL(RXD) = 15pF (≤ ±1%) | 100 | 160 | ns | |||
| 請參閱圖 6-4正常模式,VIO = 2.25V 至 2.75V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),CL(RXD) = 15pF (≤ ±1%) | 110 | 175 | ns | |||
| 請參閱圖 6-4正常模式,VIO = 1.71V 至 1.89V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),CL(RXD) = 15pF (≤ ±1%) | 125 | 190 | ns | |||
| tMODE | 模式更改時間,從正常到待機或從待機到正常 | 請參閱圖 6-5 |
30 | μs | ||
| tWK_FILTER | 有效喚醒模式的濾波時間 | 請參閱圖 7-7 | 0.5 | 0.95 | μs | |
| tWK_TIMEOUT | 總線喚醒超時值 | 請參閱圖 7-7 | 0.8 | 6 | ms | |
| Tstartup | VCC 或 VIO 清除上升欠壓閾值并且器件可以恢復(fù)正常運行之后的持續(xù)時間 | 1.5 | ms | |||
| Tfilter(STB) | 對 STB 引腳進行濾波以濾除任何干擾 | 0.5 | 1 | 2 | μs | |
| 驅(qū)動器開關(guān)特性 | ||||||
| tprop(TxD-busrec) | 傳播延遲時間,低電平到高電平的 TXD 邊沿到驅(qū)動器隱性狀態(tài)(顯性狀態(tài)到隱性狀態(tài)) | 請參閱圖 6-2 ,STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),VIO = 4.5V 至 5.5V | 35 | 70 | ns | |
| 請參閱圖 6-2 ,STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),VIO = 3V 至 3.6V | 40 | 70 | ns | |||
| 請參閱圖 6-2 ,STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),VIO = 2.25V 至 2.75V | 40 | 75 | ns | |||
| 請參閱圖 6-2 ,STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),VIO = 1.71V 至 1.89V | 42 | 80 | ns | |||
| tprop(TxD-busdom) | 傳播延遲時間,高電平到低電平的 TXD 邊沿到驅(qū)動器顯性狀態(tài)(隱性狀態(tài)到顯性狀態(tài)) | 請參閱圖 6-2 ,STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),VIO = 4.5V 至 5.5V | 35 | 75 | ns | |
| 請參閱圖 6-2 ,STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),VIO = 3V 至 3.6V | 35 | 75 | ns | |||
| 請參閱圖 6-2 ,STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),VIO = 2.25V 至 2.75V | 40 | 80 | ns | |||
| 請參閱圖 6-2 ,STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),VIO = 1.71V 至 1.89V | 42 | 80 | ns | |||
| tsk(p) | 脈沖偏斜 (|tprop(TxD-busrec) - tprop(TxD-busdom)|) | STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),請參閱圖 6-2 | 1 | 10 | ns | |
| tBUS_R | 差分輸出信號上升時間 | 請參閱圖 6-2 ,STB = 0V,45? ≤ RL ≤ 65Ω,CL = 100pF (≤ ±1%) | 15 | 30 | ns | |
| tBUS_F | 差分輸出信號下降時間 | 請參閱圖 6-2 ,STB = 0V,45? ≤ RL ≤ 65Ω,CL = 100pF (≤ ±1%) | 15 | 40 | ns | |
| tTXD_DTO | 顯性超時 | 請參閱圖 6-6 ,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),STB = 0V | 1.2 | 4.0 | ms | |
| 接收器開關(guān)特性 | ||||||
| tprop(busrec-RXD) | 傳播延遲時間,總線隱性輸入到 RXD 高電平輸出(顯性狀態(tài)到隱性狀態(tài)) | 請參閱圖 6-3 ,STB = 0V, 45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),CL(RXD) = 15pF (≤ ±1%),VIO = 4.5V 至 5.5V |
60 | 85 | ns | |
| 請參閱圖 6-3 ,STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),CL(RXD) = 15pF (≤ ±1%),VIO = 3V 至 3.6V | 65 | 95 | ns | |||
| 請參閱圖 6-3 ,STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),CL(RXD) = 15pF (≤ ±1%),VIO = 2.25V 至 2.75V | 70 | 105 | ns | |||
| 請參閱圖 6-3 ,STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),CL(RXD) = 15pF (≤ ±1%),VIO = 1.71V 至 1.89V | 80 | 110 | ns | |||
| tprop(busdom-RXD) | 傳播延遲時間,總線顯性輸入到 RXD 低電平輸出(隱性狀態(tài)到顯性狀態(tài)) | 請參閱圖 6-3 ,STB = 0V, 45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),CL(RXD) = 15pF (≤ ±1%),VIO = 4.5V 至 5.5V |
50 | 75 | ns | |
| 請參閱圖 6-3 ,STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),CL(RXD) = 15pF (≤ ±1%),VIO = 3V 至 3.6V | 60 | 80 | ns | |||
| 請參閱圖 6-3 ,STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),CL(RXD) = 15pF (≤ ±1%),VIO = 2.25V 至 2.75V | 65 | 90 | ns | |||
| 請參閱圖 6-3 ,STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),CL(RXD) = 15pF (≤ ±1%),VIO = 1.71V 至 1.89V | 80 | 110 | ns | |||
| tRXD_R | RXD 輸出信號上升時間 | 請參閱圖 6-3 ,STB = 0V, CL(RXD) = 15pF(≤ ±1%) |
8 | 25 | ns | |
| tRXD_F | RXD 輸出信號下降時間 | 7 | 30 | ns | ||
| FD 時序特性 | ||||||
| tBIT(BUS) | tBIT(TXD) = 500ns 時 CAN 總線輸出引腳上的位時間 | 請參閱圖 6-4 ,VCC = 4.5V 至 5.5V,STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF,CL(RXD) = 15pF |
490 | 510 | ns | |
| tBIT(TXD) = 200ns 時 CAN 總線輸出引腳上的位時間 | 請參閱圖 6-4 ,VCC = 4.5V 至 5.5V,STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF,CL(RXD) = 15pF |
190 | 210 | ns | ||
| tBIT(TXD) = 125ns 時 CAN 總線輸出引腳上的位時間 | 請參閱圖 6-4 ,VCC = 4.5V 至 5.5V,STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF,CL(RXD) = 15pF |
115 | 135 | ns | ||
| tBIT(RXD) | tBIT(TXD) = 500ns 時 RXD 輸出引腳上的位時間 | 請參閱圖 6-4 ,VCC = 4.75V 至 5.25V,STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF,CL(RXD) = 15pF |
470 | 520 | ns | |
| 請參閱圖 6-4 ,VCC = 4.5V 至 5.5V,STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF,CL(RXD) = 15pF |
470 | 525 | ns | |||
| tBIT(TXD) = 200ns 時 RXD 輸出引腳上的位時間 | 請參閱圖 6-4 ,VCC = 4.75V 至 5.25V,STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF,CL(RXD) = 15pF |
170 | 220 | ns | ||
| 請參閱圖 6-4 ,VCC = 4.5V 至 5.5V,STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF,CL(RXD) = 15pF |
170 | 225 | ns | |||
| tBIT(TXD) = 125ns 時 RXD 輸出引腳上的位時間 | 請參閱圖 6-4 ,VCC = 4.75V 至 5.25V,STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF,CL(RXD) = 15pF |
95 | 145 | ns | ||
| 請參閱圖 6-4 ,VCC = 4.5V 至 5.5V,STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF,CL(RXD) = 15pF |
95 | 150 | ns | |||
| 信號改善時序特性 | ||||||
| tPAS_REC_START | 被動隱性階段的 開始時間 |
從 TXD 上升 50% 邊沿(斜率 <5ns)到被動隱性階段開始的持續(xù)時間 | 420 | 530 | ns | |
| tACT_REC_START | 主動信號改善階段的開始時間 | 從 TXD 上升 50% 邊沿(斜率 <5ns)到被動隱性階段開始的持續(xù)時間 | 120 | ns | ||
| tACT_REC_END | 主動信號改善階段的結(jié)束時間 | 355 | ns | |||
| tΔBit(Bus) | 發(fā)送的位寬時間差 | VCC = 4.75V 至 5.25V,TXD <= 8Mbps,tΔBit(Bus) = tBit(Bus) - tBit(TxD) STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),CL(RXD) = 15pF (≤ ±1%),請參閱圖 6-4 |
-10 | 10 | ns | |
| VCC = 4.5V 至 5.5V,TXD <= 8Mbps,tΔBit(Bus) = tBit(Bus) - tBit(TxD) STB = 0V,RL = 60?,CL = 100pF (≤ ±1%),CL(RXD) = 15pF (≤ ±1%),請參閱圖 6-4 |
-10 | 10 | ns | |||
| tΔBIT(RxD) | 接收的位寬時間差 | VCC = 4.75V 至 5.25V,TXD <= 8Mbps,tΔBIT(RxD) = tBit(RxD) - tBit(TxD) STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),CL(RXD) = 15pF (≤ ±1%),請參閱圖 6-4 |
-30 | 20 | ns | |
| VCC = 4.5V 至 5.5V,TXD <= 8Mbps,tΔBIT(RxD) = tBit(RxD) - tBit(TxD) STB = 0V,RL = 60?,CL = 100pF (≤ ±1%),CL(RXD) = 15pF (≤ ±1%),CL(RXD) = 15pF,請參閱圖 6-4 |
-30 | 20 | ns | |||
| tΔREC | 接收器時序?qū)ΨQ性 | VCC = 4.75V 至 5.25V,TXD <= 8Mbps,tΔREC = tBit(RxD) - tBit(Bus) STB = 0V,45? ≤ RL ≤ 65?,CL = 100pF (≤ ±1%),CL(RXD) = 15pF (≤ ±1%),請參閱圖 6-4 |
-20 | 15 | ns | |
| VCC = 4.5V 至 5.5V,TXD <= 8Mbps,tΔREC = tBit(RxD) - tBit(Bus) STB = 0V,RL = 60?,CL = 100pF (≤ ±1%),CL(RXD) = 15pF (≤ ±1%),請參閱圖 6-4 |
-20 | 15 | ns | |||