ZHCSJM6A April 2019 – October 2019 TAS6421-Q1
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 說明（續(xù)）
- 6 Device Options
- 7 Pin Configuration and Functions
- 8 Specifications
- 9 Parameter Measurement Information
-
10Detailed description
- 10.1 Overview
- 10.2 Functional Block Diagram
- 10.3
Feature Description
- 10.3.1 Serial Audio Port
- 10.3.2 DC Blocking
- 10.3.3 Volume Control and Gain
- 10.3.4 High-Frequency Pulse-Width Modulator (PWM)
- 10.3.5 Gate Drive
- 10.3.6 Power FETs
- 10.3.7 Load Diagnostics
- 10.3.8
Protection and Monitoring
- 10.3.8.1 Overcurrent Limit (ILIMIT)
- 10.3.8.2 Overcurrent Shutdown (ISD)
- 10.3.8.3 DC Detect
- 10.3.8.4 Clip Detect
- 10.3.8.5 Global Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)
- 10.3.8.6 Channel Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]
- 10.3.8.7 Undervoltage (UV) and Power-On-Reset (POR)
- 10.3.8.8 Overvoltage (OV) and Load Dump
- 10.3.9 Power Supply
- 10.3.10 Hardware Control Pins
- 10.4 Device Functional Modes
- 10.5 Programming
- 10.6
Register Maps
- 10.6.1 Mode Control Register (address = 0x00) [default = 0x00]
- 10.6.2 Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]
- 10.6.3 Miscellaneous Control 2 Register (address = 0x02) [default = 0x62]
- 10.6.4 SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04]
- 10.6.5 Channel State Control Register (address = 0x04) [default = 0x55]
- 10.6.6 Channel 1 Volume Control Register (address = 0x05) [default = 0xCF]
- 10.6.7 DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]
- 10.6.8 DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]
- 10.6.9 DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]
- 10.6.10 DC Load Diagnostics Report 3 Line Output Register (address = 0x0E) [default = 0x00]
- 10.6.11 Channel State Reporting Register (address = 0x0F) [default = 0x40]
- 10.6.12 Channel Faults (Overcurrent, DC Detection) Register (address = 0x10) [default = 0x00]
- 10.6.13 Global Faults 1 Register (address = 0x11) [default = 0x00]
- 10.6.14 Global Faults 2 Register (address = 0x12) [default = 0x00]
- 10.6.15 Warnings Register (address = 0x13) [default = 0x20]
- 10.6.16 Pin Control Register (address = 0x14) [default = 0x00]
- 10.6.17 AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]
- 10.6.18 AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]
- 10.6.19 AC Load Diagnostic Impedance Report Ch1 Register (address = 0x17) [default = 0x00]
- 10.6.20 AC Load Diagnostic Phase Report High Register (address = 0x1B) [default = 0x00]
- 10.6.21 AC Load Diagnostic Phase Report Low Register (address = 0x1C) [default = 0x00]
- 10.6.22 AC Load Diagnostic STI Report High Register (address = 0x1D) [default = 0x00]
- 10.6.23 AC Load Diagnostic STI Report Low Register (address = 0x1E) [default = 0x00]
- 10.6.24 Miscellaneous Control 3 Register (address = 0x21) [default = 0x00]
- 10.6.25 Clip Control Register (address = 0x22) [default = 0x01]
- 10.6.26 Clip Window Register (address = 0x23) [default = 0x14]
- 10.6.27 Clip Warning Register (address = 0x24) [default = 0x00]
- 10.6.28 ILIMIT Status Register (address = 0x25) [default = 0x00]
- 10.6.29 Miscellaneous Control 4 Register (address = 0x26) [default = 0x40]
- 11Application and Implementation
- 12Power Supply Recommendations
- 13Layout
- 14器件和文檔支持
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DKQ|56
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DKQ|56
訂購信息
7 Pin Configuration and Functions
DKQ Package
56-Pin HSSOP With Exposed Thermal Pad
Top View
Pin Functions
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| AREF | 4 | PWR | VREG and VCOM bypass capacitor return |
| AVDD | 8 | PWR | Voltage regulator bypass. Connect 1 µF capacitor from AVDD to AVSS |
| AVSS | 7 | PWR | AVDD bypass capacitor return |
| BST_M | 44 | PWR | Bootstrap capacitor connection pin for high-side gate driver |
| BST_P | 48 | PWR | Bootstrap capacitor connection pin for high-side gate driver |
| FAULT | 26 | DO | Reports a fault (active low, open drain), 100 kΩ internal pull-up resistor |
| FSYNC | 14 | DI | Audio frame clock input |
| GND | 1, 11, 16, 17, 18, 28, 46 | GND | Ground |
| GVDD | 9 | PWR | Gate drive voltage regulator derived from VBAT input pin. Connect 2.2 µF capacitor to GND |
| I2C_ADDR0 | 22 | DI | I2C address pins. Refer to Table 7 |
| I2C_ADDR1 | 23 | ||
| MCLK | 12 | DI | Audio master clock input |
| MUTE | 25 | DI | Mutes the device outputs (active low) while keeping output FETs switching at 50%, 100 kΩ internal pull-down resistor |
| NC | 10, 29-43,
49-54 |
NC | Not connected or pulled to ground |
| OUT_M | 45 | NO | Negative output for the channel |
| OUT_P | 47 | PO | Positive output for the channel |
| PVDD | 2, 55, 56 | PWR | PVDD voltage input (can be connected to battery). Bulk capacitor and bypass capacitor required |
| SCL | 20 | DI | I2C clock input |
| SCLK | 13 | DI | Audio bit and serial clock input |
| SDA | 21 | DI/DO | I2C data input and output |
| SDIN1 | 15 | DI | TDM data input and audio I2S data input |
| STANDBY | 24 | DI | Enables low power standby state (active Low), 100 kΩ internal pull-down resistor |
| VBAT | 3 | PWR | Battery voltage input |
| VCOM | 6 | PWR | Bias voltage |
| VDD | 19 | PWR | 3.3 V external supply voltage |
| VREG | 5 | PWR | Voltage regulator bypass |
| WARN | 27 | DO | Clip and overtemperature warning (active low, open drain), 100 kΩ internal pull-up resistor |
| Thermal Pad | — | GND | Provides both electrical and thermal connection for the device. Heatsink must be connected to GND. |
(1) GND = ground, PWR = power, PO = positive output, NO = negative output, DI = digital input, DO = digital output, DI/DO = digital input and output, NC = no connection