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ZHCSJM6A April 2019 – October 2019 TAS6421-Q1

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DKQ|56
- MPDS378A

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

DKQ|56
- PPTD313E

訂購(gòu)信息

8.5 Electrical Characteristics

Test conditions (unless otherwise noted): T_C = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, R_L = 4 Ω, P_out = 1 W/ch, f_IN = 1 kHz, f_SW = 2.11 MHz, AES17 Filter, default I2C settings

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
OPERATING CURRENT
I_{PVDD_IDLE}	PVDD idle current	Channel playing, no audio input		17	23	mA
I_{VBAT_IDLE}	VBAT idle current	Channel playing, no audio input		28	32	mA
I_{PVDD_STBY}	PVDD standby current	STANDBY Active, VDD = 0 V		0.5	1	µA
I_{VBAT_STBY}	VBAT standby current	STANDBY Active, VDD = 0 V		4	6	µA
I_VDD	VDD supply current	Channel playing, –60-dB signal		15	18	mA
OUTPUT POWER
P_{O_BTL}	Output power per channel, BTL	4 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C	20	22		W
		4 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C	25	27
		2 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C	38	40
		2 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C	42	45
		4 Ω, PVDD = 25 V, THD+N = 1%, TC = 75°C	50	55
		4 Ω, PVDD = 25 V, THD+N = 10%, TC = 75°C	70	75
EFF_P	Power efficiency	1 channel operating at 25-W output power, 4 Ω load, PVDD = 14.4 V, TC = 25°C, including inductor losses		86%
AUDIO PERFORMANCE
V_n	Output noise voltage	Zero input, A-weighting, gain level 1, PVDD = 14.4 V		42		µV
		Zero input, A-weighting, gain level 2, PVDD = 14.4 V		55
		Zero input, A-weighting, gain level 3, PVDD = 18 V		67
		Zero input, A-weighting, gain level 4, PVDD = 25 V		85
GAIN	Peak Output Voltage/dBFS	gain level 1, Register 0x01, bit 1-0 = 00		7.5		V/FS
		gain level 2, Register 0x01, bit 1-0 = 01		15
		gain level 3, Register 0x01, bit 1-0 = 10		21
		gain level 4, Register 0x01, bit 1-0 = 11		29
PSRR	Power-supply rejection ratio	PVDD = 14.4 Vdc + 1 V_RMS, f = 1 kHz		75		dB
THD+N	Total harmonic distortion + noise			0.02%
LINE OUTPUT PERFORMANCE
V_{n_LINEOUT}	LINE output noise voltage	Zero input, A-weighting, channel set to LINE MODE		42		µV
V_{O_LINEOUT}	LINE output voltage	0dB input, channel set to LINE MODE		5.5		VRMS
THD+N	Line output total harmonic distortion + noise	V_O = 2 V_RMS, channel set to LINE MODE		0.01%
DIGITAL INPUT PINS
V_IH	Input logic level high		70			%VDD
V_IL	Input logic level low				30	%VDD
I_IH	Input logic current, high	V_I = VDD			15	µA
I_IL	Input logic current, low	V_I = 0			-15	µA
PWM OUTPUT STAGE
R_DS(on)	FET drain-to-source resistance	Not including bond wire and package resistance		90		mΩ
OVERVOLTAGE (OV) PROTECTION
V_{PVDD_OV}	PVDD overvoltage shutdown		27.0	27.8	28.8	V
V_{PVDD_OV_HYS}	PVDD overvoltage shutdown hysteresis			0.8		V
V_{VBAT_OV}	VBAT overvoltage shutdown		20	21.5	23	V
V_{VBAT_OV_HYS}	VBAT overvoltage shutdown hysteresis			0.6		V
UNDERVOLTAGE (UV) PROTECTION
VBAT_UV	VBAT undervoltage shutdown			4	4.5	V
VBAT_{UV_HYS}	VBAT undervoltage shutdown hysteresis			0.2		V
PVDD_UV	PVDD undervoltage shutdown			4	4.5	V
PVDD_{UV_HYS}	PVDD undervoltage shutdown hysteresis			0.2		V
BYPASS VOLTAGES
V_GVDD	Gate drive bypass pin voltage			7		V
V_AVDD	Analog bypass pin voltage			6		V
V_VCOM	Common bypass pin voltage			2.5		V
V_VREG	Regulator bypass pin voltage			5.5		V
POWER-ON RESET (POR)
V_POR	VDD voltage for POR			2.1	2.7	V
V_{POR_HYS}	VDD POR recovery hysteresis voltage			0.5		V
OVERTEMPERATURE (OT) PROTECTION
OTW_(i)	Channel overtemperature warning			150		°C
OTSD_(i)	Channel overtemperature shutdown			175		°C
OTW	Global junction overtemperature warning			130		°C
OTSD	Global junction overtemperature shutdown			160		°C
OT_HYS	Overtemperature hysteresis			15		°C
LOAD OVERCURRENT PROTECTION
I_LIM	Overcurrent cycle-by-cycle limit	OC Level 1	4.0	4.8		A
I_LIM	Overcurrent cycle-by-cycle limit	OC Level 2	6.0	6.5		A
I_SD	Overcurrent shutdown	OC Level 1, Any short to supply, ground, or other channels		7		A
I_SD	Overcurrent shutdown	OC Level 2, Any short to supply, ground, or other channels		9		A
MUTE MODE
G_MUTE	Output attenuation			100		dB
CLICK AND POP
V_CP	Output click and pop voltage	ITU-R 2k filter, High-Z/MUTE to Play, Play to Mute/High-Z		7		mV
DC OFFSET
V_OFFSET	Output offset voltage			2	5	mV
DC DETECT
DC_FAULT	Output DC fault protection			2	2.5	V
DIGITAL OUTPUT PINS
V_OH	Output voltage for logic level high	I = ±2 mA	90			%VDD
V_OL	Output voltage for logic level low	I = ±2 mA			10	%VDD
t_{DELAY_CLIPDET}	Signal delay when output clipping detected				20	µs
LOAD DIAGNOSTICS
S2P	Resistance to detect a short from OUT pin(s) to PVDD				500	Ω
S2G	Resistance to detect a short from OUT pin(s) to ground				200	Ω
SL	Shorted load detection tolerance				±0.5	Ω
OL	Open load		40	70		Ω
T_{DC_DIAG}	DC diagnostic time			100		ms
LO	Line output diagnostic detection				6	kΩ
T_{LINE_DIAG}	Line output diagnostic time	Not including the preceeding DC_DIAG time		40		ms
AC_IMP	AC impedance accuracy	Gain linearity, ƒ = 19 kHz, R_L = 2 Ω to 16 Ω			25%
AC_IMP	AC impedance accuracy	Offset			±0.5	Ω
T_{AC_DIAG}	AC diagnostic time			170		ms
I²C_ADDR PINS
t_{I2C_ADDR}	Time delay needed for I²C address set-up			300		µs
I²C CONTROL PORT
t_BUS	Bus free time between a STOP and START condition		1.3			µs
t_h1	Hold time, SCL to SDA		0			ns
t_h2	Hold time, start condition to SCL		0.6			µs
t_START	I²C startup time after VDD power on reset				12	ms
t_RISE	Rise time, SCL and SDA				300	ns
t_FALL	Fall time, SCL and SDA				300	ns
t_SU1	Setup, SDA to SCL		100			ns
t_SU2	Setup, SCL to start condition		0.6			µs
t_SU3	Setup, SCL to stop condition		0.6			µs
t_W(H)	Required pulse duration SCL High		0.6			µs
t_W(L)	Required pulse duration SCL Low		1.3			µs
SERIAL AUDIO PORT
D_MCLK, D_SCLK	Allowable input clock duty cycle		45%	50%	55%
f_MCLK	Supported MCLK frequencies	128, 256, or 512	128		512	xFS
f_{MCLK_Max}	Maximum frequency				25	MHz
t_SCY	SCLK pulse cycle time		40			ns
t_SCL	SCLK pulse-with LOW		16			ns
t_SCH	SCLK pulse-with HIGH		16			ns
t_RISE/FALL	Rise and fall time			<5		ns
t_SF	SCLK rising edge to FSYNC edge		8			ns
t_FS	FSYNC rising edge to SCLK edge		8			ns
t_DS	DATA set-up time		8			ns
t_DH	DATA hold time		8			ns
c_i	Input capacitance, pins MCLK, SCLK, FSYNC, SDIN1				10	pf
T_LA	Latency from input to output measured in FSYNC sample count	FSYNC = 44.1 kHz or 48 kHz			30
T_LA	Latency from input to output measured in FSYNC sample count	FSYNC = 96 kHz			12