ZHCSJM6A April 2019 – October 2019 TAS6421-Q1
PRODUCTION DATA.
When any kind of clock error, MCLK-FSYNC or SCLK-FSYNC ratio, or clock halt is detected, the device puts all channels into the Hi-Z state. When all audio clocks are within the expected range, the device automatically returns to the state it was in. See the Electrical Characteristics table for timing requirements.
Figure 25. Serial Audio Timing
Figure 26. Left-Justified Audio Data Format
Figure 27. I2S Audio Data Format
Figure 28. TDM8 Audio Data Format