ZHCSNB2 February 2021 SN55LVCP22A-SP
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP#ID6WFTY369A075 | MAX | UNIT | |
|---|---|---|---|---|---|---|
| CMOS/TTL DC SPECIFICATIONS (EN0, EN1, SEL0, SEL1) | ||||||
| VIH | High-level input voltage | 2 | 1.5 | VCC | V | |
| VIL | Low-level input voltage | GND | 1.5 | 0.8 | V | |
| IIH2 | High-level input current | VIN = 3.6 V or 2.0 V, VCC = 0 V | -250 | ±3 | 250 | μA |
| IIH | High-level input current | VIN = 3.6 V or 2.0 V, VCC = 3.6 V | -25 | ±3 | 25 | μA |
| IIL2 | Low-level input current | VIN = 0.0 V or 0.8 V, VCC = 0 V | -150 | ±1 | 150 | μA |
| IIL | Low-level input current | VIN = 0.0 V or 0.8 V, VCC = 3.6 V | -15 | ±1 | 15 | μA |
| VCL | Input clamp voltage | ICL = –18 mA | -0.8 | -1.5 | V | |
| LVDS OUTPUT SPECIFICATIONS (OUT0, OUT1) | ||||||
| |VOD| | Differential output voltage | RL = 75 ?, See GUID-DFC33E3A-CD0C-47EA-9546-39403915B952.html#IDOKZO-D3XRHU | 255 | 390 | 475 | mV |
| RL = 75 ?, VCC = 3.3 V, TA = 25°C, See GUID-DFC33E3A-CD0C-47EA-9546-39403915B952.html#IDOKZO-D3XRHU | 320 | 390 | 430 | |||
| Δ|VOD| | Change in differential output voltage magnitude between logic states | VID = ±100 mV, See GUID-DFC33E3A-CD0C-47EA-9546-39403915B952.html#IDOKZO-D3XRHU | –25 | 25 | mV | |
| VOS | Steady-state offset voltage | See GUID-DFC33E3A-CD0C-47EA-9546-39403915B952.html#IDUMZO-3AXRHU | 1 | 1.2 | 1.45 | V |
| ΔVOS | Change in steady-state offset voltage between logic states | See GUID-DFC33E3A-CD0C-47EA-9546-39403915B952.html#IDUMZO-3AXRHU | –25 | 25 | mV | |
| VOC(PP) | Peak-to-peak common-mode output voltage | See GUID-DFC33E3A-CD0C-47EA-9546-39403915B952.html#IDUMZO-3AXRHU | 50 | mV | ||
| IOZ | High-impedance output current | VOUT = GND or VCC | -15 | 15 | μA | |
| IOFF | Power-off leakage current | VCC = 0 V, 1.5 V; VOUT = 3.6 V or GND | -15 | 15 | μA | |
| IOZH | High-impedance output current, after HDR 100 krad | VOUT = VCC, TA = 25°C | -120 | 350 | μA | |
| IOFFH | Power-off leakage current, after after HDR 100 krad | VCC = 0 V, 1.5 V; VOUT = 3.6 V, TA = 25°C | -50 | 150 | μA | |
| IOS | Output short-circuit current | VOUT+ or VOUT- = 0 V | -8 | mA | ||
| IOSB | Both outputs short-circuit current | VOUT+ and VOUT- = 0 V | –8 | 8 | mA | |
| CO | Differential output capacitance | VI = 0.4 sin(4E6πt) + 0.5 V | 3 | pF | ||
| LVDS RECEIVER DC SPECIFICATIONS (IN0, IN1) | ||||||
| VTH | Positive-going differential input voltage threshold | See GUID-DFC33E3A-CD0C-47EA-9546-39403915B952.html#IDFNZO-104XRHU and Table 7-1 | 100 | mV | ||
| VTL | Negative-going differential input voltage threshold | See GUID-DFC33E3A-CD0C-47EA-9546-39403915B952.html#IDFNZO-104XRHU and Table 7-1 | –100 | mV | ||
| VID(HYS) | Differential input voltage hysteresis | 20 | 150 | mV | ||
| VCMR | Common-mode voltage range | VID = 100 mV, VCC = 3.0 V to 3.6 V | 0.05 | 3.95 | V | |
| IIN | Input current | VIN = 4 V, VCC = 3.6 V or 0.0 | -18 | ±1 | 18 | μA |
| VIN = 0 V, VCC = 3.6V or 0.0 | -18 | ±1 | 18 | |||
| CIN | Differential input capacitance | VI = 0.4 sin (4E6πt) + 0.5 V | 3 | pF | ||
| SUPPLY CURRENT | ||||||
| ICCQ | Quiescent supply current | RL = 75 ?, EN0=EN1=High | 60 | 87 | mA | |
| ICCD | Total supply current | RL = 75 ?, CL = 5 pF, 500 MHz (1000 Mbps), EN0=EN1=High | 63 | 87 | mA | |
| ICCZ | 3-state supply current | EN0 = EN1 = Low | 25 | 35 | mA | |