SLES248A May 2009 – March 2015 PCM1795
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1
Mode Control Registers
- 7.6.1.1 User-Programmable Mode Controls
- 7.6.1.2 Register Map
- 7.6.1.3
Register Definitions
- 7.6.1.3.1 R/W: Read/Write Mode Select
- 7.6.1.3.2 ATx[7:0]: Digital Attenuation Level Setting
- 7.6.1.3.3 R/W: Read/Write Mode Select
- 7.6.1.3.4 ATLD: Attenuation Load Control
- 7.6.1.3.5 FMT[2:0]: Audio Interface Data Format
- 7.6.1.3.6 DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function
- 7.6.1.3.7 DME: Digital De-Emphasis Control
- 7.6.1.3.8 MUTE: Soft Mute Control
- 7.6.1.3.9 R/W: Read/Write Mode Select
- 7.6.1.3.10 REV: Output Phase Reversal
- 7.6.1.3.11 ATS[1:0]: Attenuation Rate Select
- 7.6.1.3.12 OPE: DAC Operation Control
- 7.6.1.3.13 DFMS: Stereo DF Bypass Mode Select
- 7.6.1.3.14 FLT: Digital Filter Roll-Off Control
- 7.6.1.3.15 INZD: Infinite Zero Detect Mute Control
- 7.6.1.3.16 R/W: Read/Write Mode Select
- 7.6.1.3.17 SRST: System Reset Control
- 7.6.1.3.18 DSD: DSD Interface Mode Control
- 7.6.1.3.19 DFTH: Digital Filter Bypass (or Through Mode) Control
- 7.6.1.3.20 MONO: Monaural Mode Selection
- 7.6.1.3.21 CHSL: Channel Selection for Monaural Mode
- 7.6.1.3.22 OS[1:0]: ΔΣ Oversampling Rate Selection
- 7.6.1.3.23 R/W: Read/Write Mode Select
- 7.6.1.3.24 DZ[1:0]: DSD Zero Output Enable
- 7.6.1.3.25 PCMZ: PCM Zero Output Enable
- 7.6.1.3.26 R: Read Mode Select
- 7.6.1.3.27 ZFGx: Zero-Detection Flag
- 7.6.1.3.28 Read Mode Select
- 7.6.1.3.29 ID[4:0]: Device ID
- 7.6.1
Mode Control Registers
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Applications
- 8.2.1 Typical Connection Diagram in PCM Mode
- 8.2.2
Application for External Digital Filter Interface
- 8.2.2.1 Design Requirements
- 8.2.2.2 Detailed Design Procedure
- 8.2.2.3 Application Curves
- 8.2.3 Application for DSD Format (DSD Mode) Interface
- 8.2.4
TDMCA Interface Format
- 8.2.4.1 Design Requirements
- 8.2.4.2
Detailed Design Procedure
- 8.2.4.2.1 TDMCA Mode Determination
- 8.2.4.2.2 TDMCA Terminals
- 8.2.4.2.3 Device ID Determination
- 8.2.4.2.4 TDMCA Frame
- 8.2.4.2.5
Command Field
- 8.2.4.2.5.1 Bit 31: Device ID Enable Flag
- 8.2.4.2.5.2 Bit 30: Extended Command Enable Flag
- 8.2.4.2.5.3 Bit 29: Daisy-Chain Selection Flag
- 8.2.4.2.5.4 Bits[28:24]: Device ID
- 8.2.4.2.5.5 Bit 23: Command Read/Write flag
- 8.2.4.2.5.6 Bits[22:16]: Register ID
- 8.2.4.2.5.7 Bits[15:8]: Command data
- 8.2.4.2.5.8 Bits[7:0]: Not used
- 8.2.4.2.6 Extended Command Field
- 8.2.4.2.7 Audio Fields
- 8.2.4.2.8 TDMCA Register Requirements
- 8.2.4.2.9 Register Write/Read Operation
- 8.2.4.2.10 TDMCA Mode Operation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DB|28
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
5 Pin Configuration and Functions
DB Package
28-Pin SSOP
(Top View)
Pin Functions
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| AGND1 | 19 | — | Analog ground (internal bias) |
| AGND2 | 24 | — | Analog ground (internal bias) |
| AGND3L | 27 | — | Analog ground (left channel DACFF) |
| AGND3R | 16 | — | Analog ground (right channel DACFF) |
| BCK | 6 | Input | Bit clock input(1) |
| DATA | 5 | Input | Serial audio data input(1) |
| DGND | 8 | — | Digital ground |
| IOUTL+ | 25 | Output | Left channel analog current output+ |
| IOUTL– | 26 | Output | Left channel analog current output– |
| IOUTR+ | 17 | Output | Right channel analog current output+ |
| IOUTR– | 18 | Output | Right channel analog current output– |
| IREF | 20 | — | Output current reference bias pin |
| LRCK | 4 | Input | Left and right clock (fS) input(1) |
| MC | 12 | Input | Mode control clock input(1) |
| MDI | 11 | Input | Mode control data input(1) |
| MDO | 13 | Input or Output | Mode control read-back data output(3) |
| MS | 10 | Input or Output | Mode control chip-select input(2); active low |
| MSEL | 3 | Input | I2C/SPI select(1); active low SPI select |
| RST | 14 | Input | Reset(1); active low |
| SCK | 7 | Input | System clock input(1) |
| VCC1 | 23 | — | Analog power supply, 5 V |
| VCC2L | 28 | — | Analog power supply (left channel DACFF), 5 V |
| VCC2R | 15 | — | Analog power supply (right channel DACFF), 5 V |
| VCOML | 22 | — | Left channel internal bias decoupling pin |
| VCOMR | 21 | — | Right channel internal bias decoupling pin |
| VDD | 9 | — | Digital power supply, 3.3 V |
| ZEROL | 1 | Input or Output | Zero flag for left channel(2) |
| ZEROR | 2 | Input or Output | Zero flag for right channel(2) |
(1) Schmitt-trigger input, 5-V tolerant.
(2) Schmitt-trigger input and output. 5-V tolerant input and CMOS output.
(3) Schmitt-trigger input and output. 5-V tolerant input. In I2C mode, this pin becomes an open-drain 3-state output; otherwise, this pin is a CMOS output.