8.2.1.2.1 I/V Section

The current of the PCM1795 device on each of the output pins (I_OUTL+, I_OUTL–, I_OUTR+, I_OUTR–) is 4 mA_PP at 0 dB (full-scale). The voltage output level of the current-to-voltage (I/V) converter, V_I, is given by Equation 2.

An NE5534 operational amplifier is recommended for the I/V circuit to obtain the specified performance. Dynamic performance such as the gain bandwidth, settling time, and slew rate of the operational amplifier affects the audio dynamic performance of the I/V section.

8.2.1.2.2 Differential Section

The PCM1795 device voltage outputs are followed by differential amplifier stages that sum the differential signals for each channel, creating a single-ended I/V op-amp output. In addition, the differential amplifiers provide a low-pass filter function.

The operational amplifier recommended for the differential circuit is the low-noise type.

Figure 53. Measurement Circuit for PCM

Figure 54. Measurement Circuit for DSD

(1) Circuit corresponds to Figure 53.

Figure 55. Measurement Circuit for Monaural Mode

8.2.2.2.1 Application for Interfacing With an External Digital Filter

For some applications, it may be desirable to use an external digital filter to perform the interpolation function, as it can provide improved stop-band attenuation when compared to the internal digital filter of the PCM1795 device.

The PCM1795 device supports several external digital filters, including:

• Texas Instruments DF1704 and DF1706
• Pacific Microsonics PMD200 HDCD filter/decoder IC
• Programmable DSPs

The external digital filter application mode is accessed by programming the following bits in the corresponding control register:

• DFTH = 1 (register 20)

The pins used to provide the serial interface for the external digital filter are illustrated in Figure 58. The word clock (WDCK) signal must be operated at 8 times or 4 times the desired sampling frequency, f_S.

8.2.2.2.2 Pin Assignment When Using the External Digital Filter Interface

• LRCK (pin 4): WDCK as word clock input
• BCK (pin 6): Bit clock for audio data
• DATA (pin 5): Monaural audio data input when the DFMS bit is not set to 1
• ZEROL (pin 1): DATAL as left channel audio data input when the DFMS bit is set to 1
• ZEROR (pin 2): DATAR as right channel audio data input when the DFMS bit is set to 1

8.2.2.2.3 Audio Format

The PCM1795 device in the external digital filter interface mode supports right-justified audio formats including 16-bit, 24-bit, and 32-bit audio data, as shown in Figure 59. The audio format is selected by the FMT[2:0] bits of control register 18.

Figure 59. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application

8.2.2.2.4 System Clock (SCK) and Interface Timing

The PCM1795 device in an application using an external digital filter requires the synchronization of WDCK and the system clock. The system clock is phase-free with respect to WDCK. Interface timing among WDCK, BCK, DATA, DATAL, and DATAR is shown in Figure 60 and Table 32.

Figure 60. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application

8.2.2.2.5 Functions Available in the External Digital Filter Mode

The external digital filter mode is selected by setting DSD = 0 (register 20, B5) and DFTH = 1 (register 20, B4).

The external digital filter mode allows access to the majority of the PCM1795 mode control functions.

Table 33 shows the register mapping available when the external digital filter mode is selected, along with descriptions of functions that are modified when using this mode selection.

8.2.3.2.1 Features

This mode is used for interfacing directly to a DSD decoder, which is found in Super Audio CD™ (SACD) applications.

The DSD mode is accessed by programming the following bit in the corresponding control register.

• DSD = 1 (register 20)

The DSD mode provides a low-pass filtering function. The filtering is provided using an analog FIR filter structure. Four FIR responses are available and are selected by the DMF[1:0] bits of control register 18.

The DSD bit must be set before inputting DSD data; otherwise, the PCM1795 erroneously detects the TDMCA mode and commands are not accepted through the serial control interface.

8.2.3.2.2 Pin Assignment When Using DSD Format Interface

Several pins are redefined for DSD mode operation. These include:

• DATA (pin 5): DSDL as left-channel DSD data input
• LRCK (pin 4): DSDR as right-channel DSD data input
• SCK (pin 7): DBCK as bit clock for DSD data
• BCK (pin 6): Set low (N/A)

8.2.3.2.3 Requirements for System Clock

For operation in DSD mode, the bit clock (DBCK) is required on pin 7 of the PCM1795. The frequency of the bit clock can be N times the sampling frequency. Generally, N is 64 in DSD applications.

The interface timing between the bit clock and DSDL and DSDR is required to meet the setup and hold time specifications shown in Figure 65 and Table 36.

Figure 64. Normal Data Output Form From DSD Decoder

Figure 65. Timing for DSD Audio Interface

8.2.3.2.4 DSD Mode Configuration and Function Controls

8.2.4.2.1 TDMCA Mode Determination

The PCM1795 device recognizes the TDMCA mode automatically when it receives an LRCK signal with a pulse duration of two BCK clocks. If the TDMCA mode operation is not needed, the duty cycle of LRCK must be 50%. Figure 69 shows the LRCK and BCK timing that determines the TDMCA mode. The PCM1795 device enters TDMCA mode after two continuous TDMCA frames. Any TDMCA commands can be issued during the next TDMCA frame after entering TDMCA mode.

Figure 69. LRCK and BCK Timing for Determination of TDMCA Mode

8.2.4.2.2 TDMCA Terminals

TDMCA requires six signals: four signals are for the command and audio data interface, and one pair for daisy-chaining. These signals can be shared as shown in Table 40. The DO signal has a 3-state output so that it can be connected directly to other devices.

8.2.4.2.3 Device ID Determination

TDMCA mode also supports a multichip implementation in one system. This capability means that a host controller (DSP) can simultaneously support several TDMCA devices, which can be of the same type or different types, including PCM devices. The PCM devices are categorized as either IN devices, OUT devices, IN/OUT devices, and NO devices. The IN device has an input port to receive audio data; the OUT device has an output port to supply audio data; the IN/OUT device has both input and output ports for audio data; and the NO device has no port for audio data, but requires command data from the host. A DAC is an IN device; an ADC is an OUT device; a codec is an IN/OUT device; and a PLL is a NO device. The PCM1795 is an IN device. For the host controller to distinguish the devices, each device is assigned its own device ID by the daisy-chain. The devices obtain their own device IDs automatically by connecting the DCI to the DCO of the preceding device and the DCO to the DCI of the following device in the daisy-chain. The daisy-chains are categorized as the IN chain and the OUT chain, which are completely independent and equivalent. Figure 70 shows an example daisy-chain connection. If a system must chain the PCM1795 device and a NO device in the same IN or OUT chain, the NO device must be chained at the back end of the chain because it does not require any audio data. Figure 71 shows an example TDMCA system including an IN chain and an OUT chain with a TI DSP. For a device to get its own device ID, the DID signal must be set to '1' (see the Command Field section for details), and LRCK and BCK must be driven in the TDMCA mode for all PCM devices that are chained. The device at the top of the chain knows its device ID is '1' because its DCI is fixed high. Other devices count the BCK pulses and observe the respective DCI signal to determine ID and position in the chain. Figure 72 shows the initialization of each device ID.

Figure 70. Daisy-Chain Connection Example

Figure 71. IN Daisy-Chain and OUT Daisy-Chain Connection Example for a Multichip System

Figure 72. Device ID Determination Sequence

8.2.4.2.4 TDMCA Frame

In general, the TDMCA frame consists of the command field, extended command (EMD) field, and audio data fields. All fields are 32 bits long, but the lowest byte has no meaning. The MSB is transferred first for each field. The command field is always transferred as the first packet of the frame. The EMD field is transferred if the EMD flag of the command field is high. If any EMD packets are transferred, no audio data follow the EMD packets. This frame is for quick system initialization. All devices of a daisy-chain should respond to the command field and extended command field. The PCM1795 has two audio channels that can be selected by OPE (register 19). If the OPE bit is not set to high, those audio channels are transferred. Figure 73 shows the general TDMCA frame. If some DACs are enabled, but corresponding audio data packets are not transferred, the analog outputs are unpredictable.

Figure 73. General TDMCA Frame

Figure 74. TDMCA Frame Example of Six-Channel DAC and Two-Channel ADC With Command Read

8.2.4.2.5 Command Field

The normal command field is defined as shown in Figure 75. When the DID bit (MSB) is '1', this frame is used only for device ID determination, and all remaining bits in the field are ignored.

Figure 75. Normal Command Field

8.2.4.2.6 Extended Command Field

The extended command field is the same as the command field, except that it does not have a DID flag. Figure 76 defines the extended command field.

Figure 76. Extended Command Field

8.2.4.2.7 Audio Fields

The audio field is 32 bits long and the audio data are transferred MSB first, so the other fields must be filled with 0s as shown in Figure 77.

Figure 77. Audio Field Example

8.2.4.2.8 TDMCA Register Requirements

The TDMCA mode requires device ID and audio channel information, as previously described. The OPE bit in register 19 indicates audio channel availability and register 23 indicates the device ID. Register 23 is used only in the TDMCA mode; see the mode control register map of Table 10.

8.2.4.2.9 Register Write/Read Operation

The command supports register write and read operations. If the command requests to read one register, the read data are transferred on DO during the data phase of the timing cycle. The DI signal can be retrieved at the positive edge of BCK, and the DO signal is driven at the negative edge of BCK. DO is activated one BCK cycle early to compensate for the output delay caused by high impedance. Figure 78 shows the TDMCA write and read timing.

Figure 78. TDMCA Write and Read Operation Timing

8.2.4.2.10 TDMCA Mode Operation

DCO specifies the owner of the next audio channel in TDMCA mode operation. When a device retrieves its own audio channel data, DCO goes high during the last audio channel period. Figure 79 shows the DCO output timing in TDMCA mode operation. The host controller ignores the behavior of DCI and DCO. DCO indicates the last audio channel of each device. Therefore, DCI means the next audio channel is allocated.

If some devices are skipped because of no active audio channel, the skipped devices must notify the next device that the DCO will be passed through the next DCI. Figure 80 and Figure 81 show DCO timing with skip operation. Figure 82 and Table 41 show the ac timing of the daisy-chain signals.

Figure 79. DCO Output Timing of TDMCA Mode Operation

Figure 80. DCO Output Timing With Skip Operation

Figure 81. DCO Output Timing With Skip Operation (for Command Packet 1)

Figure 82. AC Timing of Daisy-Chain Signals