ZHCSXH5K December 2005 – December 2024 PCA9557
PRODUCTION DATA
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| STANDARD MODE | ||||
| fscl | I2C clock frequency | 100 | kHz | |
| tsch | I2C clock high time | 4 | μs | |
| tscl | I2C clock low time | 4.7 | μs | |
| tsp | I2C spike time | 50 | ns | |
| tsds | I2C serial data setup time | 250 | ns | |
| tsdh | I2C serial data hold time | 0 | ns | |
| ticr | I2C input rise time | 1000 | ns | |
| ticf | I2C input fall time | 300 | ns | |
| tocf | I2C output fall time, 10-pF to 400-pF bus | 300 | ns | |
| tbuf | I2C bus free time between stop and start | 4.7 | μs | |
| tsts | I2C start or repeated start condition setup time | 4.7 | μs | |
| tsth | I2C start or repeated start condition hold time | 4 | μs | |
| tsps | I2C stop condition setup time | 4 | μs | |
| tvd(data) | Valid data time, SCL low to SDA output valid | 1 | μs | |
| tvd(ack) | Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low | 1 | μs | |
| Cb | I2C bus capacitive load | 400 | pF | |
| FAST MODE | ||||
| fscl | I2C clock frequency | 400 | kHz | |
| tsch | I2C clock high time | 0.6 | μs | |
| tscl | I2C clock low time | 1.3 | μs | |
| tsp | I2C spike time | 50 | ns | |
| tsds | I2C serial data setup time | 100 | ns | |
| tsdh | I2C serial data hold time | 0 | ns | |
| ticr | I2C input rise time | 20 + 0.1Cb (1) | 300 | ns |
| ticf | I2C input fall time | 20 + 0.1Cb (1) | 300 | ns |
| tocf | I2C output fall time, 10-pF to 400-pF bus | 20 + 0.1Cb (1) | 300 | ns |
| tbuf | I2C bus free time between Stop and Start | 1.3 | μs | |
| tsts | I2C start or repeated start condition setup time | 0.6 | μs | |
| tsth | I2C start or repeated start condition hold time | 0.6 | μs | |
| tsps | I2C stop condition setup time | 0.6 | μs | |
| tvd(data) | Valid data time, SCL low to SDA output valid | 0.9 | μs | |
| tvd(ack) | Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low | 0.9 | μs | |
| Cb | I2C bus capacitive load | 400 | pF | |