4 Pin Configuration and Functions

Figure 4-1 D, DB, DGV, PW Package, 16-Pin SOIC, SSOP, TVSOP, or TSSOP (Top View)

Figure 4-2 RGY or RGV Package, 16-Pin VQFN or VQFN (Top View)

Table 4-1 Pin Functions

PIN		TYPE⁽¹⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾	DESCRIPTION
SCL	1	I	Serial clock bus. Connect to V_CC through a pullup resistor.
SDA	2	I/O	Serial data bus. Connect to V_CC through a pullup resistor.
A0	3	I	Address input. Connect directly to V_CC or ground.
A1	4	I	Address input. Connect directly to V_CC or ground.
A2	5	I	Address input. Connect directly to V_CC or ground.
P0	6	I/O	P-port input/output. High impedance open-drain design structure. Connect to V_CC through a pullup resistor.
P1	7	I/O	P-port input/output. Push-pull design structure
GND	8	G	Ground
P2	9	I/O	P-port input/output. Push-pull design structure
P3	10	I/O	P-port input/output. Push-pull design structure
P4	11	I/O	P-port input/output. Push-pull design structure
P5	12	I/O	P-port input/output. Push-pull design structure
P6	13	I/O	P-port input/output. Push-pull design structure
P7	14	I/O	P-port input/output. Push-pull design structure
RESET	15	I	Active-low reset input. Connect to V_CC through a pullup resistor if no active connection is used.
V_CC	16	P	Supply voltage

(1) I = input, O = output, P = power, G = Ground

Figure 4-3 RGV Package, 16-Pin QFN (Top View)

Table 4-2 Pin Functions, RGV

PIN		TYPE⁽¹⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾	DESCRIPTION
A0	1	I	Address input. Connect directly to V_CC or ground.
A1	2	I	Address input. Connect directly to V_CC or ground.
A2	3	I	Address input. Connect directly to V_CC or ground.
P0	4	I/O	P-port input/output. High impedance open-drain design structure. Connect to V_CC through a pullup resistor.
P1	5	I/O	P-port input/output. Push-pull design structure
GND	6	G	Ground
P2	7	I/O	P-port input/output. Push-pull design structure
P3	8	I/O	P-port input/output. Push-pull design structure
P4	9	I/O	P-port input/output. Push-pull design structure
P5	10	I/O	P-port input/output. Push-pull design structure
P6	11	I/O	P-port input/output. Push-pull design structure
P7	12	I/O	P-port input/output. Push-pull design structure
RESET	13	I	Active-low reset input. Connect to V_CC through a pullup resistor if no active connection is used.
V_CC	14	P	Supply voltage
SCL	15	I	Serial clock bus. Connect to V_CC through a pullup resistor.
SDA	16	I/O	Serial data bus. Connect to V_CC through a pullup resistor.

(1) I = input, O = output, P = power, G = Ground