SNVSB23 March 2018 LP87521-Q1 , LP87522-Q1 , LP87523-Q1 , LP87524-Q1 , LP87525-Q1
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Address: 0x22
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| Reserved | RESET_REG
_MASK |
||||||
| Bits | Field | Type | Default | Description |
|---|---|---|---|---|
| 7:1 | Reserved | R/W | 0h | |
| 0 | RESET_REG_MASK | R/W | X | Masking for the register reset interrupt (the RESET_REG bit in the INT_TOP2 register)
0h = Interrupt generated 1h = Interrupt not generated |