SNVSB23 March 2018 LP87521-Q1 , LP87522-Q1 , LP87523-Q1 , LP87524-Q1 , LP87525-Q1
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Address: 0x1A
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| Reserved | INT_BUCK23 | INT_BUCK01 | NO_SYNC_CLK | TDIE_SD | TDIE_WARN | INT_OVP | I_LOAD_
READY |
| Bits | Field | Type | Default | Description |
|---|---|---|---|---|
| 7 | Reserved | R/W | 0h | |
| 6 | INT_BUCK23 | R | 0h | Interrupt indicating that the output of the BUCK3 regulator,BUCK2 regulator, or both regulators has a pending interrupt. The reason for the interrupt is indicated in the INT_BUCK_2_3 register.
This bit is cleared automatically when the INT_BUCK_2_3 register is cleared to 0x00. |
| 5 | INT_BUCK01 | R | 0h | Interrupt indicating that the output of the BUCK1 regulator, BUCK0 regulator, or both regulators has a pending interrupt. The reason for the interrupt is indicated in the INT_BUCK_0_1 register.
This bit is cleared automatically when the INT_BUCK_0_1 register is cleared to 0x00. |
| 4 | NO_SYNC_CLK | R/W1C | 0h | Latched status bit indicating that the external clock is not valid.
Write this bit to 1h to clear the interrupt. |
| 3 | TDIE_SD | R/W1C | 0h | Latched status bit indicating that the die junction temperature is greater than the thermal shutdown level. The regulators are disabled if previously enabled. The regulators cannot be enabled if this bit is active. The actual status of the thermal warning condition is indicated by the TDIE_SD_STAT bit in the TOP_STAT register.
Write this bit to 1h to clear the interrupt. |
| 2 | TDIE_WARN | R/W1C | 0h | Latched status bit indicating that the die junction temperature is greater than the thermal warning level. The actual status of the thermal warning condition is indicated by the TDIE_WARN_STAT bit in the TOP_STAT register.
Write this bit to 1h to clear the interrupt. |
| 1 | INT_OVP | R/W1C | 0h | Latched status bit indicating that the input voltage is greater than the overvoltage-detection level. The actual status of the overvoltage condition is indicated by the OVP_STAT bit in the OP_STAT register.
Write this bit to 1h to clear the interrupt. |
| 0 | I_LOAD_READY | R/W1C | 0h | Latched status bit indicating that the load-current measurement result is available in the I_LOAD_1 and I_LOAD_2 registers.
Write this bit to 1h to clear the interrupt. |