SNVSB23 March 2018 LP87521-Q1 , LP87522-Q1 , LP87523-Q1 , LP87524-Q1 , LP87525-Q1
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Address: 0x08
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| EN_BUCK3 | EN_PIN_CTRL3 | BUCK3_EN_PIN_SELECT[1:0] | EN_ROOF_FLOOR3 | EN_RDIS3 | BUCK3_FPWM | Reserved | |
| Bits | Field | Type | Default | Description |
|---|---|---|---|---|
| 7 | EN_BUCK3 | R/W | X | This bit enables the BUCK3 regulator.
0h = BUCK3 regulator is disabled 1h = BUCK3 regulator is enabled |
| 6 | EN_PIN_CTRL3 | R/W | X | This bit enables the EN1, EN2, EN3 pin control for the BUCK3 regulator.
0h = Only the EN_BUCK3 bit controls the BUCK3 regulator 1h = EN_BUCK3 bit AND ENx pin control the BUCK3 regulator |
| 5:4 | BUCK3_EN_PIN_SELECT[1:0] | R/W | X | This bit enables the EN1, EN2, EN3 pin control for the BUCK3 regulator.
0h = EN_BUCK3 bit AND EN1 pin control the BUCK3 regulator 1h = EN_BUCK3 bit AND EN2 pin control the BUCK3 regulator 2h = EN_BUCK3 bit AND EN3 pin control the BUCK3 regulator 3h = Reserved |
| 3 | EN_ROOF_FLOOR3 | R/W | 0h | This bit enables the roof and floor control of EN1, EN2, EN3 pin if the EN_PIN_CTRL3 bit is set to 1h.
0h = Enable and disable (1/0) control 1h = Roof and floor (1/0) control |
| 2 | EN_RDIS3 | R/W | 1h | This bit enables the output discharge resistor when the BUCK3 regulator is disabled.
0h = Discharge resistor disabled 1h = Discharge resistor enabled |
| 1 | BUCK3_FPWM | R/W | X | This bit forces the BUCK3 regulator to operate in PWM mode.
0h = Automatic transitions between PFM and PWM modes (AUTO mode) 1h = Forced to PWM operation |
| 0 | Reserved | R/W | 0h |