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SNVS234C September 2004 – September 2016 LM5112 , LM5112-Q1

PRODUCTION DATA.

封裝選項

請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機械數(shù)據(jù) (封裝 | 引腳)

NGG|6
DGN|8

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

	MIN	MAX	UNIT
V_CC to V_EE	–0.3	15	V
V_CC to IN_REF	–0.3	15	V
IN/INB to IN_REF	–0.3	15	V
IN_REF to V_EE	–0.3	5	V
Maximum junction temperature		150	°C
Operating junction temperature	–40	125	°C
Storage temperature, T_stg	–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
V_CC	Operating voltage, V_CC – IN_REF and V_CC – V_EE		3.5	14	V
	Operating junction temperature		–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LM5112, LM5112-Q1		UNIT
		NGG (WSON)	DGN (MSOP PowerPAD)
		6 PINS	8 PINS
R_θJA	Junction-to-ambient thermal resistance	40	53.7	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	50.8	61.1	°C/W
R_θJB	Junction-to-board thermal resistance	29.3	37.2	°C/W
ψ_JT	Junction-to-top characterization parameter	0.7	7.2	°C/W
ψ_JB	Junction-to-board characterization parameter	29.5	36.9	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	7.5	4.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

T_J = –40°C to 125°C, V_CC = 12 V, INB = IN_REF = V_EE = 0 V, and no Load on output (unless otherwise noted).

PARAMETER		CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY
V_CC	Operating voltage	V_CC – IN_REF and V_CC – V_EE	3.5		14	V
UVLO	Undervoltage lockout (rising)	V_CC – IN_REF	2.4	3	3.5	V
V_CCH	Undervoltage hysteresis			230		mV
I_CC	Supply current			1	2	mA
CONTROL INPUTS
V_IH	Logic high		2.3			V
V_IL	Logic low				0.8	V
V_thH	High threshold		1.3	1.75	2.3	V
V_thL	Low threshold		0.8	1.35	2	V
HYS	Input hysteresis			400		mV
I_IL	Input current low	IN = INB = 0 V	–1	0.1	1	µA
I_IH	Input current high	IN = INB = V_CC	–1	0.1	1	µA
OUTPUT DRIVER
R_OH	Output resistance high	I_OUT = –10 mA⁽¹⁾		30	50	Ω
R_OL	Output resistance low	I_OUT = 10 mA⁽¹⁾		1.4	2.5	Ω
I_SOURCE	Peak source current	OUT = V_CC / 2,200 ns pulsed current		3		A
I_SINK	Peak sink current	OUT = V_CC / 2,200 ns pulsed current		7		A
LATCHUP PROTECTION
	AEC–Q100, METHOD 004	T_J = 150°C		500		mA

(1) The output resistance specification applies to the MOS device only. The total output current capability is the sum of the MOS and bipolar devices.

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
td1	Propagation delay time low to high, IN or INB rising (IN to OUT)	C_LOAD = 2 nF, see Figure 13	25	40	ns
td2	Propagation delay time high to low, IN or INB falling (IN to OUT)	C_LOAD = 2 nF, see Figure 13	25	40	ns
tr	Rise time	C_LOAD = 2 nF, see Figure 13	14		ns
tf	Fall time	C_LOAD = 2 nF, see Figure 13	12		ns