ZHCSDT0C june 2015 – may 2023 ISO5851
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| VCC1 | Supply voltage input side | 3 | 5.5 | V | |
| VCC2 | Positive supply voltage output side (VCC2 – GND2) | 15 | 30 | V | |
| VEE2 | Negative supply voltage output side (VEE2 – GND2) | –15 | 0 | V | |
| V(SUP2) | Total supply voltage output side (VCC2 – VEE2) | 15 | 30 | V | |
| VIH | High-level input voltage (IN+, IN–, RST) | 0.7 × VCC1 | VCC1 | V | |
| VIL | Low-level input voltage (IN+, IN–, RST) | 0 | 0.3 × VCC1 | V | |
| tUI | Pulse width at IN+, IN– for full output (CLOAD = 1 nF) | 40 | ns | ||
| tRST | Pulse width at RST for resetting fault latch | 800 | ns | ||
| TA | Ambient temperature | –40 | 25 | 125 | °C |