If the power supply voltage on the PVDD pin exceeds the VPVDD_OV threshold for longer than the tPVDD_OV_DG time, the DRV871x-Q1 detects a PVDD overvoltage condition and action is taken according to the PVDD_OV_MODE register setting. The overvoltage threshold and deglitch time can be adjusted through the PVDD_OV_LVL and PVDD_OV_DG register settings.
On SPI device variants, the PVDD overvoltage monitor can respond and recover in four different modes set through the PVDD_OV_MODE register setting.
- Latched Fault Mode: After detecting the overvoltage condition, the gate driver pull downs are enabled and nFAULT pin, FAULT register bit, and PVDD_OV register bit asserted. After the overvoltage condition is removed, the fault state remains latched until CLR_FLT is issued.
- Automatic Recovery Mode: After detecting the overvoltage condition, the gate driver pull downs are enabled and nFAULT pin, FAULT register bit, and PVDD_OV register bit asserted. After the overvoltage condition is removed, the nFAULT pin and FAULT register bit are automatically cleared and the driver automatically reenabled. The PVDD_OV register bit remains latched until CLR_FLT is issued.
- Warning Report Only Mode: The PVDD overvoltage condition is reported in the WARN and PVDD_OV register bits. The device will not take any action. The warning remains latched until CLR_FLT is issued.
- Disabled Mode: The PVDD overvoltage monitor is disabled and will not respond or report.
On H/W device variants, the PVDD overvoltage monitor is disabled.