ZHCSN08D August 2020 – April 2024 DRV8714-Q1 , DRV8718-Q1
PRODMIX
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 External Components
- 7.3.2 Device Interface Variants
- 7.3.3 Input PWM Control Modes
- 7.3.4 Smart Gate Driver
- 7.3.5 Tripler (Dual-Stage) Charge Pump
- 7.3.6 Wide Common-Mode Current Shunt Amplifiers
- 7.3.7 Pin Diagrams
- 7.3.8
Protection and Diagnostics
- 7.3.8.1 Gate Driver Disable (DRVOFF/nFLT and EN_DRV)
- 7.3.8.2 Low IQ Powered Off Braking (POB, BRAKE)
- 7.3.8.3 Fault Reset (CLR_FLT)
- 7.3.8.4 DVDD Logic Supply Power on Reset (DVDD_POR)
- 7.3.8.5 PVDD Supply Undervoltage Monitor (PVDD_UV)
- 7.3.8.6 PVDD Supply Overvoltage Monitor (PVDD_OV)
- 7.3.8.7 VCP Charge Pump Undervoltage Lockout (VCP_UV)
- 7.3.8.8 MOSFET VDS Overcurrent Protection (VDS_OCP)
- 7.3.8.9 Gate Driver Fault (VGS_GDF)
- 7.3.8.10 Thermal Warning (OTW)
- 7.3.8.11 Thermal Shutdown (OTSD)
- 7.3.8.12 Offline Short Circuit and Open Load Detection (OOL and OSC)
- 7.3.8.13 Watchdog Timer
- 7.3.8.14 Fault Detection and Response Summary Table
- 7.4 Device Functional Modes
- 7.5 Programming
- 8 Register Maps
- 9 Application Implementation
- 10Device Documentation and Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據 (封裝 | 引腳)
散熱焊盤機械數(shù)據 (封裝 | 引腳)
訂購信息
5.2 VQFN (RHA) 40-Pin Package and Pin Functions
Figure 5-3 DRV8714S-Q1 VQFN (RHA) 40-Pin
Package Top View 
Figure 5-4 DRV8714H-Q1 VQFN (RHA) 40-Pin
Package Top ViewTable 5-2 VQFN (RHA) 40-Pin Package Pin Functions
| PIN | I/O | TYPE | DESCRIPTION | ||
|---|---|---|---|---|---|
| NO. | NAME | ||||
| DRV8714S-Q1 | DRV8714H-Q1 | ||||
| 1 | SDI | — | I | Digital | Serial data input. Data is captured on the falling edge of the SCLK pin. Internal pulldown resistor. |
| — | IDRIVE | I | Analog | Gate driver output current setting. 6 level input pin set by an external resistor. | |
| 2 | SDO | — | O | Digital | Serial data output. Data is shifted out on the rising edge of the SCLK pin. Push-pull output. |
| — | MODE | I | Analog | Analog PWM input mode setting. 4 level input pin set by an external resistor. | |
| 3 | IN1/EN1 | I | Digital | Half-bridge and H-bridge control input. See Section 7.3.3. Internal pulldown. | |
| 4 | IN2/PH1 | I | Digital | ||
| 5 | IN3/EN2 | I | Digital | ||
| 6 | IN4/PH2 | I | Digital | ||
| 7 | nSLEEP | I | Digital | Device enable pin. Logic low to shutdown the device and enter sleep mode. Internal pulldown resistor. | |
| 8 | DRVOFF/nFLT | — | I/O | Digital | Multi-function pin for either driver shutdown input or fault indicator output. See Section 7.3.8. Internal pulldown resistor. |
| — | nFLT | O | Digital | Fault indicator output. This pin is pulled logic low to indicate a fault condition. Open-drain output. Requires external pullup resistor. | |
| 9 | SO1 | O | Analog | Shunt amplifier output. | |
| 10 | SO2 | O | Analog | Shunt amplifier output. | |
| 11 | BRAKE | I | Digital | Powered off braking pin. Logic high to enable low-side gate drivers while in low-power sleep mode. See Section 7.3.8.2. Internal pulldown resistor. | |
| 12 | SP1 | I | Analog | Amplifier positive input. Connect to positive terminal of the shunt resistor. | |
| 13 | SN1 | I | Analog | Amplifier negative input. Connect to negative terminal of the shunt resistor. | |
| 14 | SP2 | I | Analog | Amplifier positive input. Connect to positive terminal of the shunt resistor. | |
| 15 | SN2 | I | Analog | Amplifier negative input. Connect to negative terminal of the shunt resistor. | |
| 16 | GH1 | O | Analog | High-side gate driver output. Connect to the gate of the high-side MOSFET. | |
| 17 | SH1 | I | Analog | High-side source sense input. Connect to the high-side MOSFET source. | |
| 18 | GL1 | O | Analog | Low-side gate driver output. Connect to the gate of the low-side MOSFET. | |
| 19 | PGND1 | I | Analog | Low-side MOSFET gate drive 1-2 sense and power return. Connect to system ground close to the device and half-bridge 1-2. | |
| 20 | GL2 | O | Analog | Low-side gate driver output. Connect to the gate of the low-side MOSFET. | |
| 21 | SH2 | I | Analog | High-side source sense input. Connect to the high-side MOSFET source. | |
| 22 | GH2 | O | Analog | High-side gate driver output. Connect to the gate of the high-side MOSFET. | |
| 23 | CP2L | I/O | Power | Charge pump switching node. Connect a 100nF, PVDD-rated ceramic capacitor between the CP2H and CP2L pins. | |
| 24 | CP2H | I/O | Power | ||
| 25 | CP1L | I/O | Power | Charge pump switching node. Connect a 100nF, PVDD-rated ceramic capacitor between the CP1H and CP1L pins. | |
| 26 | CP1H | I/O | Power | ||
| 27 | VCP | I/O | Power | Charge pump output. Connect a 1μF, 16V ceramic capacitor between the VCP and PVDD pins. | |
| 28 | PVDD | I | Power | Device driver power supply input. Connect to the bridge power supply. Connect a 0.1μF, PVDD-rated ceramic capacitor and local bulk capacitance greater than or equal to 10μF between PVDD and GND pins. | |
| 29 | DRAIN | I | Analog | Bridge MOSFET drain voltage sense pin. Connect to common point of the high-side MOSFET drains. | |
| 30 | GH3 | O | Analog | High-side gate driver output. Connect to the gate of the high-side MOSFET. | |
| 31 | SH3 | I | Analog | High-side source sense input. Connect to the high-side MOSFET source. | |
| 32 | GL3 | O | Analog | Low-side gate driver output. Connect to the gate of the low-side MOSFET. | |
| 33 | PGND2 | I | Analog | Low-side MOSFET gate drive 3-4 sense and power return. Connect to system ground close to the device and half-bridge 3-4. | |
| 34 | GL4 | O | Analog | Low-side gate driver output. Connect to the gate of the low-side MOSFET. | |
| 35 | SH4 | I | Analog | High-side source sense input. Connect to the high-side MOSFET source. | |
| 36 | GH4 | O | Analog | High-side gate driver output. Connect to the gate of the high-side MOSFET. | |
| 37 | GND | I/O | Ground | Device ground. Connect to system ground. | |
| 38 | DVDD | I | Power | Device logic and digital output power supply input. External voltage reference and power supply for current sense amplifiers. Recommended to connect a 1.0μF, 6.3V ceramic capacitor between the DVDD and GND pins. | |
| 39 | nSCS | — | I | Digital | Serial chip select. A logic low on this pin enables serial interface communication. Internal pullup resistor. |
| — | GAIN | I | Analog | Amplifier gain setting. 4 level input pin set by an external resistor. | |
| 40 | SCLK | — | I | Digital | Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. Internal pulldown resistor. |
| — | VDS | I | Analog | VDS monitor threshold setting. 6 level input pin set by an external resistor. | |